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? 2000 data sheet description the pd780021a, 780022a, 780023a, and 780024a are members of the pd780024a subseries of the 78k/0 series. only selected functions of the existing pd78054 subseries are provided, and the serial interface is enhanced. the pd780021ay, 780022ay, 780023ay, and 780024ay are the pd780024a subseries with a multimaster supporting i 2 c bus interface, which makes them suitable for av equipment. flash memory versions, the pd78f0034a, 78f0034b, 78f0034ay, and 78f0034by, that can operate in the same power supply voltage range as the mask rom versions, and various development tools, are also available. detailed function descriptions are provided in the following user? manuals. be sure to read them before designing. pd780024a, 780034a, 780024ay, 780034ay subseries user? manual: u14046e 78k/0 series instructions user? manual: u12326e features internal rom and ram item program memory data memory package part number (internal rom) (internal high-speed ram) pd780021a, 780021ay 8 kb 512 bytes ? 64-pin plastic sdip (19.05 mm (750)) pd780022a, 780022ay 16 kb ? 64-pin plastic qfp (14 x 14) ? 64-pin plastic lqfp (14 x 14) pd780023a, 780023ay 24 kb 1024 bytes ? 64-pin plastic tqfp (12 x 12) pd780024a, 780024ay 32 kb ? 64-pin plastic lqfp (10 x 10) ? 73-pin plastic fbga (9 x 9) external memory expansion space: 64 kb minimum instruction execution time expanded-specification products of pd780021a, 780022a, 780023a, 780024a: 0.166 s (f x = 12 mhz, v dd = 4.5 to 5.5 v) pd780021ay, 780022ay, 780023ay, 780024ay and conventional products of pd780021a, 780022a, 780023a, 780024a: 0.238 s (f x = 8.38 mhz, v dd = 4.0 to 5.5 v) i/o ports: 51 (n-ch open-drain (5 v withstanding voltage): 4) 8-bit resolution a/d converter: 8 channels (av dd = 1.8 to 5.5 v) serial interface: 3 channels pd780021a, 780022a, 780023a, 780024a: uart mode, 3-wire serial i/o mode (2 channels) pd780021ay, 780022ay, 780023ay, 780024ay: uart mode, 3-wire serial i/o mode, i 2 c bus mode timer: 5 channels power supply voltage: v dd = 1.8 to 5.5 v 8-bit single-chip microcontrollers mos integrated circuit pd780021a, 780022a, 780023a, 780024a 780021ay, 780022ay, 780023ay, 780024ay the mark shows major revised points. document no. u14042ej4v0ds00 (4th edition) date published december 2002 n cp(k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. .com .com .com 4 .com u datasheet
2 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds applications telephones, household electrical appliances, pagers, av equipment, car audios, office automation equipment, etc. ordering information (1/2) (1) pd780024a subseries part number package pd780021acw- 64-pin plastic sdip (19.05 mm (750)) pd780021agc- -ab8 64-pin plastic qfp (14 x 14) pd780021agc- -8bs 64-pin plastic lqfp (14 x 14) pd780021agk- -9et 64-pin plastic tqfp (12 x 12) pd780021agb- -8eu 64-pin plastic lqfp (10 x 10) pd780021af1- -cn3 73-pin plastic fbga (9 x 9) pd780022acw- 64-pin plastic sdip (19.05 mm (750)) pd780022agc- -ab8 64-pin plastic qfp (14 x 14) pd780022agc- -8bs 64-pin plastic lqfp (14 x 14) pd780022agk- -9et 64-pin plastic tqfp (12 x 12) pd780022agb- -8eu 64-pin plastic lqfp (10 x 10) pd780022af1- -cn3 73-pin plastic fbga (9 x 9) pd780023acw- 64-pin plastic sdip (19.05 mm (750)) pd780023agc- -ab8 64-pin plastic qfp (14 x 14) pd780023agc- -8bs 64-pin plastic lqfp (14 x 14) pd780023agk- -9et 64-pin plastic tqfp (12 x 12) pd780023agb- -8eu 64-pin plastic lqfp (10 x 10) pd780023af1- -cn3 73-pin plastic fbga (9 x 9) pd780024acw- 64-pin plastic sdip (19.05 mm (750)) pd780024agc- -ab8 64-pin plastic qfp (14 x 14) pd780024agc- -8bs 64-pin plastic lqfp (14 x 14) pd780024agk- -9et 64-pin plastic tqfp (12 x 12) pd780024agb- -8eu 64-pin plastic lqfp (10 x 10) pd780024af1- -cn3 73-pin plastic fbga (9 x 9) remark indicates rom code suffix. .com .com .com .com 4 .com u datasheet
3 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds ordering information (2/2) (2) pd780024ay subseries part number package pd780021aycw- 64-pin plastic sdip (19.05 mm (750)) pd780021aygc- -ab8 64-pin plastic qfp (14 x 14) pd780021aygc- -8bs 64-pin plastic lqfp (14 x 14) pd780021aygk- -9et 64-pin plastic tqfp (12 x 12) pd780021aygb- -8eu 64-pin plastic lqfp (10 x 10) pd780021ayf1- -cn3 73-pin plastic fbga (9 x 9) pd780022aycw- 64-pin plastic sdip (19.05 mm (750)) pd780022aygc- -ab8 64-pin plastic qfp (14 x 14) pd780022aygc- -8bs 64-pin plastic lqfp (14 x 14) pd780022aygk- -9et 64-pin plastic tqfp (12 x 12) pd780022aygb- -8eu 64-pin plastic lqfp (10 x 10) pd780022ayf1- -cn3 73-pin plastic fbga (9 x 9) pd780023aycw- 64-pin plastic sdip (19.05 mm (750)) pd780023aygc- -ab8 64-pin plastic qfp (14 x 14) pd780023aygc- -8bs 64-pin plastic lqfp (14 x 14) pd780023aygk- -9et 64-pin plastic tqfp (12 x 12) pd780023aygb- -8eu 64-pin plastic lqfp (10 x 10) pd780023ayf1- -cn3 73-pin plastic fbga (9 x 9) pd780024aycw- 64-pin plastic sdip (19.05 mm (750)) pd780024aygc- -ab8 64-pin plastic qfp (14 x 14) pd780024aygc- -8bs 64-pin plastic lqfp (14 x 14) pd780024aygk- -9et 64-pin plastic tqfp (12 x 12) pd780024aygb- -8eu 64-pin plastic lqfp (10 x 10) pd780024ayf1- -cn3 73-pin plastic fbga (9 x 9) remark indicates rom code suffix. .com .com .com .com 4 .com u datasheet
4 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds expanded-specification products and conventional products the expanded-specification product and conventional product refer to the following products. expanded-specification product: pd780021a, 780022a, 780023a, 780024a for which orders were received after december 1, 2001. (products with a rank note other than k, e, p, x) conventional product: products other than the above expanded specification products. (products with rank note k, e, p, x) pd780021ay, 780022ay, 780023ay, 780024ay note the rank is indicated by the 5th digit from the left in the lot number marked on the package. expanded-specification products and conventional products differ in the power supply voltage range and operating frequency ratings. power supply voltage (v dd ) guaranteed operating speed (operating frequency) conventional products expanded-specification products 4.5 to 5.5 v 8.38 mhz (0.238 s) 12 mhz (0.166 s) 4.0 to 5.5 v 8.38 mhz (0.238 s) 8.38 mhz (0.238 s) 3.0 to 5.5 v 5 mhz (0.4 s) 8.38 mhz (0.238 s) 2.7 to 5.5 v 5 mhz (0.4 s) 5 mhz (0.4 s) 1.8 to 5.5 v 1.25 mhz (1.6 s) 1.25 mhz (1.6 s) remark the parenthesized values indicates the minimum instruction execution time. correspondence between mask rom products and flash memory products mask rom products flash memory products expanded-specification products of pd780021a, pd78f0034b 780022a, 780023a, 780024a conventional products of pd780021a, 780022a, pd78f0034a 780023a, 780024a pd780021ay, 780022ay, 780023ay, 780024ay pd78f0034ay, 78f0034by remark the pd78f0034a and 78f0034b differ in the operating frequency ratings and communication mode of flash memory programming. the pd78f0034ay and 78f0034by only differ in the communication mode of flash memory programming. refer to the data sheet of the products. lot number year code rank week code nec electronics control code .com .com .com .com 4 .com u datasheet
5 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds 78k/0 series lineup the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries names. remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are same. pd78083 pd78018f pd78018fy pd78014h emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) 42/44-pin 64-pin 64-pin 52-pin 52-pin version of the pd780024a pd780024as 52-pin 52-pin version of the pd780034a pd780034as pd78054 with iebus tm controller pd78054 with enhanced serial i/o pd78078y with enhanced serial i/o and limited function pd78054 with timer and enhanced external interface 64-pin 64-pin 80-pin 80-pin 80-pin emi-noise reduced version of the pd78054 pd78018f with uart and d/a converter, and enhanced i/o pd780034a pd780988 pd780034ay 64-pin pd780024a with expanded ram pd780024a with enhanced a/d converter on-chip inverter control circuit and uart. emi-noise reduced. pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series lcd drive pd78064 with enhanced sio, and expanded rom and ram emi-noise reduced version of the pd78064 basic subseries for driving lcds, on-chip uart bus interface supported pd78018f with enhanced serial i/o 80-pin 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. romless version of the pd78078 100-pin 100-pin emi-noise reduced version of the pd78078 inverter control pd780208 100-pin vfd drive pd78044f with enhanced i/o and vfd c/d. display output total: 53 pd78098b 100-pin pd780024a pd780024ay 80-pin 80-pin pd780852 pd780828b for automobile meter driver. on-chip can controller 100-pin pd780958 for industrial meter control on-chip automobile meter controller/driver meter control 80-pin on-chip iebus controller 80-pin on-chip controller compliant with j1850 (class 2) pd780833y pd780948 on-chip can controller 64-pin pd780078 pd780078y pd780034a with timer and enhanced serial i/o pd78054 pd78054y pd78058f pd78058fy pd780058 pd780058y pd78070a pd78070ay pd78078 pd78078y pd780018ay control pd78075b pd780065 pd78044h pd780232 80-pin 80-pin for panel control. on-chip vfd c/d. display output total: 53 pd78044f with n-ch open-drain i/o. display output total: 34 pd78044f 80-pin basic subseries for driving vfd. display output total: 34 120-pin pd780308 with enhanced display function and timer. segment signal output: 40 pins max. pd780318 pd780328 120-pin 120-pin pd780308 with enhanced display function and timer. segment signal output: 32 pins max. pd780308 with enhanced display function and timer. segment signal output: 24 pins max. pd780338 pd780308 with enhanced display function and timer. segment signal output: 40 pins max. on-chip can controller specialized for can controller function 80-pin pd780703y pd780702y 64-pin pd780816 pd780344 with enhanced a/d converter 100-pin 100-pin pd780344 pd780344y pd780354 pd780354y .com .com .com .com 4 .com u datasheet
6 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds the major functional differences among the subseries are listed below. ? non-y subseries function rom timer 8-bit 10-bit 8-bit serial interface i/o external subseries name 8-bit 16-bit watch wdt a/d a/d d/a expansion control pd78075b 32 k to 40 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch) 88 1.8 v pd78078 48 k to 60 k pd78070a 61 2.7 v pd780058 24 k to 60 k 2 ch 3 ch (time-division uart: 1 ch) 68 1.8 v pd78058f 48 k to 60 k 3 ch (uart: 1 ch) 69 2.7 v pd78054 16 k to 60 k 2.0 v pd780065 40 k to 48 k 4 ch (uart: 1 ch) 60 2.7 v pd780078 48 k to 60 k 2 ch 8 ch 3 ch (uart: 2 ch) 52 1.8 v pd780034a 8 k to 32 k 1 ch 3 ch (uart: 1 ch) 51 pd780024a 8 ch pd780034as ? ch 39 pd780024as 4 ch pd78014h 8 ch 2 ch 53 pd78018f 8 k to 60 k pd78083 8 k to 16 k 1 ch (uart: 1 ch) 33 inverter pd780988 16 k to 60 k 3 ch note 1 ch 8 ch 3 ch (uart: 2 ch) 47 4.0 v control vfd pd780208 32 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2.7 v drive pd780232 16 k to 24 k 3 ch 4 ch 40 4.5 v pd78044h 32 k to 48 k 2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 v pd78044f 16 k to 40 k 2 ch lcd pd780354 24 k to 32 k 4 ch 1 ch 1 ch 1 ch 8 ch 3 ch (uart: 1 ch) 66 1.8 v drive pd780344 8 ch pd780338 48 k to 60 k 3 ch 2 ch 10 ch 1 ch 2 ch (uart: 1 ch) 54 pd780328 62 pd780318 70 pd780308 48 k to 60 k 2 ch 1 ch 8 ch 3 ch (time-division uart: 1 ch) 57 2.0 v pd78064b 32 k 2 ch (uart: 1 ch) pd78064 16 k to 32 k bus pd780948 60 k 2 ch 2 ch 1 ch 1 ch 8 ch 3 ch (uart: 1 ch) 79 4.0 v interface pd78098b 40 k to 60 k 1 ch 2 ch 69 2.7 v supported pd780816 32 k to 60 k 2 ch 12 ch 2 ch (uart: 1 ch) 46 4.0 v meter pd780958 48 k to 60 k 4 ch 2 ch 1 ch 2 ch (uart: 1 ch) 69 2.2 v control dash- pd780852 32 k to 40 k 3 ch 1 ch 1 ch 1 ch 5 ch 3 ch (uart: 1 ch) 56 4.0 v board control pd780828b 32 k to 60 k 59 note 16-bit timer: 2 channels 10-bit timer: 1 channel v dd min. value capacity (bytes) .com .com .com .com 4 .com u datasheet
7 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds ? ? ? ? ? y subseries function timer 8-bit 10-bit 8-bit serial interface i/o external subseries name 8-bit 16-bit watch wdt a/d a/d d/a expansion control pd78078y 48 k to 60 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch, i 2 c: 1 ch) 88 1.8 v pd78070ay 61 2.7 v pd780018ay 48 k to 60 k 3 ch (i 2 c: 1 ch) 88 pd780058y 24 k to 60 k 2 ch 2 ch 3 ch (time-division uart: 1 ch, i 2 c: 1 ch ) 68 1.8 v pd78058fy 48 k to 60 k 3 ch (uart: 1 ch, i 2 c: 1 ch) 69 2.7 v pd78054y 16 k to 60 k 2.0 v pd780078y 48 k to 60 k 2 ch 8 ch 4 ch (uart: 2 ch, i 2 c: 1 ch) 52 1.8 v pd780034ay 8 k to 32 k 1 ch 3 ch (uart: 1 ch, i 2 c: 1 ch) 51 pd780024ay 8 ch pd78018fy 8 k to 60 k 2 ch (i 2 c: 1 ch) 53 lcd pd780354y 24 k to 32 k 4 ch 1 ch 1 ch 1 ch 8 ch 4 ch (uart: 1 ch, 66 1.8 v drive pd780344y 8 ch i 2 c: 1 ch) pd780308y 48 k to 60 k 2 ch 3 ch (time-division uart: 1 ch, i 2 c: 1 ch) 57 2.0 v pd78064y 16 k to 32 k 2 ch (uart: 1 ch, i 2 c: 1 ch) bus pd780701y 60 k 3 ch 2 ch 1 ch 1 ch 16 ch 4 ch (uart: 1 ch, i 2 c: 1 ch) 67 3.5 v interface pd780703y supported pd780833y 65 4.5 v remark the functions of non-y subseries and y subseries products are the same, except for the serial interface. v dd min. value rom capacity (bytes) .com .com .com .com 4 .com u datasheet
8 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds overview of functions (1/2) part number pd780021a pd780022a pd780023a pd780024a item pd780021ay pd780022ay pd780023ay pd780024ay internal rom 8 kb 16 kb 24 kb 32 kb memory high-speed ram 512 bytes 1024 bytes memory space 64 kb general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution on-chip minimum instruction execution time cycle variable function when main system ?expanded-specification products of pd780021a, 780022a, 780023a, 780024a: clock selected 0.166 s/0.333 s/0.666 s/1.33 s/2.66 s (@12 mhz, v dd = 4.5 to 5.5 v operation) pd780021ay, 780022ay, 780023ay, 780024ay and conventional products of pd780021a, 780022a, 780023a, 780024a: 0.238 s/0.48 s/0.95 s/1.91 s/3.81 s (@8.38 mhz, v dd = 4.0 to 5.5 v operation) when subsystem 122 s (@ 32.768 khz operation) clock selected instruction set ?16-bit operation ?multiply/divide (8 bits 8 bits,16 bits 8 bits) ?bit manipulation (set, reset, test, boolean operation) ?bcd adjust, etc. i/o ports total: 51 ?cmos input: 8 ?cmos i/o: 39 ?n-ch open-drain i/o (5 v withstanding voltage): 4 a/d converter ?8-bit resolution 8 channels ?low-voltage operation available: av dd = 1.8 to 5.5 v serial interface ? pd780021a, 780022a, 780023a, 780024a uart mode: 1 channel 3-wire serial i/o mode: 2 channels ? pd780021ay, 780022ay, 780023ay, 780024ay uart mode: 1 channel 3-wire serial i/o mode: 1 channel i 2 c bus mode (multimaster supporting): 1 channel timers ?16-bit timer/event counter: 1 channel ?8-bit timer/event counter: 2 channels ?watch timer: 1 channel ?watchdog timer: 1 channel timer outputs 3 (8-bit pwm output capable: 2) time .com .com .com .com 4 .com u datasheet
9 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds overview of functions (2/2) part number pd780021a pd780022a pd780023a pd780024a item pd780021ay pd780022ay pd780023ay pd780024ay clock output ?expanded-specification products of pd780021a, 780022a, 780023a, 780024a: 93.75 khz, 187.5 khz, 375 khz, 750 khz, 1.25 mhz, 3 mhz, 6 mhz, 12 mhz (@12mhz operation with main system clock) 32.768 khz (@ 32.768 khz operation with subsystem clock) pd780021ay, 780022ay, 780023ay, 780024ay and conventional products of pd780021a, 780022a, 780023a, 780024a: 65.5 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (@ 8.38 mhz operation with main system clock) 32.768 khz (@ 32.768 khz operation with subsystem clock) buzzer output ?expanded-specification products of pd780021a, 780022a, 780023a, 780024a: 1.46 khz, 2.93 khz, 5.86 khz, 11.7 khz (@ 12 mhz operation with main system clock) ? pd780021ay, 780022ay, 780023ay, 780024ay and conventional products of pd780021a, 780022a, 780023a, 780024a: 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz (@ 8.38 mhz operation with main system clock) vectored maskable internal: 13, external: 5 interrupt non-maskable internal: 1 sources software 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ?0 to +85 c package ?64-pin plastic sdip (19.05 mm (750)) ?64-pin plastic qfp (14 x 14) ?64-pin plastic lqfp (14 x 14) ?64-pin plastic tqfp (12 x 12) ?64-pin plastic lqfp (10 x 10) ?73-pin plastic fbga (9 x 9) .com .com .com .com 4 .com u datasheet
10 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds contents 1. pin configuration (top view) ................................................................................................. 11 2. block diagram .............................................................................................................................15 3. pin functions ................................................................................................................ ................16 3.1 port pins ............................................................................................................................... ..................... 16 3.2 non-port pins ............................................................................................................................... ............. 17 3.3 pin i/o circuits and recommended connection of unused pins ..................................................... 19 4. memory space ................................................................................................................. ..............21 5. peripheral hardware function features ...................................................................... 22 5.1 ports ............................................................................................................................... ............................ 22 5.2 clock generator ............................................................................................................................... ......... 23 5.3 timer/counter ............................................................................................................................... ............ 24 5.4 clock output/buzzer output controller ................................................................................................ 28 5.5 a/d converter ............................................................................................................................... ............ 29 5.6 serial interface ............................................................................................................................... ........... 30 6. interrupt functions .......................................................................................................... .......33 7. external device expansion function ...............................................................................36 8. standby function .......................................................................................................................36 9. reset function ............................................................................................................................36 10. mask option ............................................................................................................................... ....36 11. instruction set ............................................................................................................. ..............37 12. electrical specifications ......................................................................................................39 12.1 expanded-specification products of pd780021a, 780022a, 780023a, 780024a .......................... 39 12.2 pd780021ay, 780022ay, 780023ay, 780024ay, and conventional products of pd780021a, 780022a, 780023a, 780024a ............................................................................................................................... ..... 55 12.3 timing chart ............................................................................................................................... ............... 71 13. package drawings .....................................................................................................................77 14. recommended soldering conditions ................................................................................83 appendix a. development tools ................................................................................................87 appendix b. related documents ...............................................................................................91 .com .com .com .com 4 .com u datasheet
11 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds 1. pin configuration (top view) 64-pin plastic sdip (19.05 mm (750)) notes 1. sda0 and scl0 are incorporated only in the pd780024ay subseries. 2. si31, so31, and sck31 are incorporated only in the pd780024a subseries. cautions 1. connect the ic (internally connected) pin directly to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remark when the pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, and 780024ay are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p67/astb p66/wait p65/wr p64/rd p75/buz p74/pcl p73/ti51/to51 p72/ti50/to50 p71/ti01 p70/ti00/to0 p03/intp3/adtrg p02/intp2 p01/intp1 p00/intp0 v ss1 x1 x2 ic xt1 xt2 reset av dd av ref p10/ani0 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v ss0 v dd0 p30 p31 p32/sda0 note 1 p33/scl0 note 1 p34/si31 note 2 p35/so31 note 2 p36/sck31 note 2 p20/si30 p21/so30 p22/sck30 p23/rxd0 p24/txd0 p25/asck0 v dd1 .com .com .com .com 4 .com u datasheet
12 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds 64-pin plastic qfp (14 x 14) 64-pin plastic lqfp (14 x 14) 64-pin plastic tqfp (12 x 12) 64-pin plastic lqfp (10 x 10) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v ss0 v dd0 p30 p31 p32/sda0 note 1 p33/scl0 note 1 p34/si31 note 2 p35/so31 note 2 p36/sck31 note 2 p20/si30 p21/so30 p22/sck30 p23/rxd0 p24/txd0 p25/asck0 v dd1 av ss p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p71/ti01 p70/ti00/to0 p03/intp3/adtrg p02/intp2 p01/intp1 p00/intp0 v ss1 x1 x2 ic xt1 xt2 reset av dd av ref p10/ani0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p67/astb p66/wait p65/wr p64/rd p75/buz p74/pcl p73/ti51/to51 p72/ti50/to50 notes 1. sda0 and scl0 are incorporated only in the pd780024ay subseries. 2. si31, so31, and sck31 are incorporated only in the pd780024a subseries. cautions 1. connect the ic (internally connected) pin directory to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remark when the pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, and 780024ay are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. .com .com .com .com 4 .com u datasheet
13 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds pin no . pin name pin no . pin name pin no . pin name pin no . pin name pin no . pin name a1 nc c1 p52/a10 e1 p57/a15 g1 p33/scl0 note 1 j1 nc a2 p46/ad6 c2 p53/a11 e2 v dd0 g2 p32/sda0 note 1 j2 p36/sck31 note 2 a3 p44/ad4 c3 p45/ad5 e3 p54/a12 g3 p20/si30 j3 nc a4 p41/ad1 c4 p42/ad2 e4 ? g4 p21/so30 j4 p25/asck0 a5 p67/astb c5 p64/rd e5 ? g5 p24/txd0 j5 nc a6 p65/wr c6 p73/ti51/to51 e6 ? g6 v dd1 j6 p17/ani7 a7 p74/pcl c7 p03/intp3/adtrg e7 p00/intp0 g7 p16/ani6 j7 p12/ani2 a8 nc c8 p01/intp1 e8 xt1 g8 av dd j8 p13/ani3 a9 nc c9 v ss1 e9 x2 g9 nc j9 nc b1 p51/a9 d1 p55/a13 f1 p30 h1 p34/si31 note 2 b2 p47/ad7 d2 p56/a14 f2 p31 h2 p35/so31 note 2 b3 p43/ad3 d3 p50/a8 f3 v ss0 h3 p23/rxd0 b4 p40/ad0 d4 nc f4 ? h4 p22/sck30 b5 p66/wait d5 ? f5 ? h5 av ss b6 p75/buz d6 ? f6 ? h6 p15/ani5 b7 p72/ti50/to51 d7 p02/intp2 f7 p14/ani4 h7 p11/ani1 b8 p71/ti01 d8 ic f8 reset h8 p10/ani0 b9 p70/ti00/to0 d9 x1 f9 xt2 h9 av ref notes 1. sda0 and scl0 are incorporated only in the pd780024ay subseries. 2. si31, so31, and sck31 are incorporated only in the pd780024a subseries. cautions 1. connect the ic (internally connected) pin directory to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remark when the pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, and 780024ay are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 73-pin plastic fbga (9 x 9) top view bottom view jhgfedcba abcdefghj 9 8 7 6 5 4 3 2 1 index mark .com .com .com .com 4 .com u datasheet
14 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds p64 to p67: port 6 p70 to p75: port 7 pcl: programmable clock rd: read strobe reset: reset rxd0: receive data sck30, sck31, scl0: serial clock sda0: serial data si30, si31: serial input so30, so31: serial output ti00, ti01, ti50, ti51: timer input to0, to50, to51: timer output txd0: transmit data v dd0 , v dd1 : power supply v ss0 , v ss1 : ground wait: wait wr: write strobe x1, x2: crystal (main system clock) xt1, xt2: crystal (subsystem clock) a8 to a15: address bus ad0 to ad7: address/data bus adtrg: ad trigger input ani0 to ani7: analog input asck0: asynchronous serial clock astb: address strobe av dd : analog power supply av ref : analog reference voltage av ss : analog ground buz: buzzer clock ic: internally connected intp0 to intp3: external interrupt input nc: no connection p00 to p03: port 0 p10 to p17: port 1 p20 to p25: port 2 p30 to p36: port 3 p40 to p47: port 4 p50 to p57: port 5 .com .com .com .com 4 .com u datasheet
15 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds 2. block diagram notes 1. incorporated only in the pd780024a subseries. 2. incorporated only in the pd780024ay subseries. remark the internal rom and ram capacities vary depending on the product. ti00/to0/p70 16-bit timer/ event counter serial interface 30 interrupt control buzzer output clock output control 78k/0 cpu core port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 p70 to p75 p64 to p67 p50 to p57 p40 to p47 p30 to p36 p20 to p25 p10 to p17 p00 to p03 external access system control reset x1 x2 xt1 xt2 rd/p64 wr/p65 wait/p66 astb/p67 ad0/p40 to ad7/p47 a8/p50 to a15/p57 rom ram a/d converter uart0 v dd0 v dd1 v ss0 v ss1 ic watchdog timer watch timer 8-bit timer/ event counter 50 8-bit timer/ event counter 51 ti50/to50/p72 ti51/to51/p73 si30/p20 so30/p21 sck30/p22 rxd0/p23 txd0/p24 asck0/p25 av dd av ss av ref buz/p75 pcl/p74 ani0/p10 to ani7/p17 intp0/p00 to intp3/p03 ti01/p71 serial interface 31 note 1 si31/p34 so31/p35 sck31/p36 sda0/p32 i 2 c bus note 2 scl0/p33 .com .com .com .com 4 .com u datasheet
16 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds 3. pin functions 3.1 port pins (1/2) pin name i/o function after alternate reset function p00 to p02 i/o port 0 input intp0 to 4-bit i/o port intp2 p03 input/output can be specified in 1-bit units. intp3/adtrg an on-chip pull-up resistor can be used by setting software. p10 to p17 input port 1 input ani0 to ani7 8-bit input only port p20 i/o port 2 input si30 p21 6-bit i/o port so30 p22 input/output can be specified in 1-bit units. sck30 p23 an on-chip pull-up resistor can be used by setting software. rxd0 p24 txd0 p25 asck0 p30 i/o port 3 n-ch open-drain i/o port input p31 7-bit i/o port an on-chip pull-up resistor can be p32 input/output can be specified in specified by the mask option. sda0 note 1 p33 1-bit units. leds can be driven directly. scl0 note 1 p34 an on-chip pull-up resistor can be si31 note 2 p35 used by setting software. so31 note 2 p36 sck31 note 2 p40 to p47 i/o port 4 input ad0 to ad7 8-bit i/o port input/output can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. the interrupt request flag (krif) is set to 1 by falling edge detection. p50 to p57 i/o port 5 input a8 to a15 8-bit i/o port leds can be driven directly. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. p64 i/o port 6 input rd p65 4-bit i/o port wr p66 input/output can be specified in 1-bit units. wait p67 an on-chip pull-up resistor can be used by setting software. astb notes 1. sda0 and scl0 are incorporated only in the pd780024ay subseries. 2. si31, so31, and sck31 are incorporated only in the pd780024a subseries. .com .com .com .com 4 .com u datasheet
17 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds 3.1 port pins (2/2) pin name i/o function after alternate reset function p70 i/o port 7 input ti00/to0 p71 6-bit i/o port ti01 p72 input/output can be specified in 1-bit units. ti50/to50 p73 an on-chip pull-up resistor can be used by setting software. ti51/to51 p74 pcl p75 buz 3.2 non-port pins (1/2) pin name i/o function after alternate reset function intp0 input external interrupt request input for which the valid edge (rising edge, input p00 intp2 falling edge, or both rising and falling edges) can be specified p01 intp2 p02 intp3 p03/adtrg si30 input serial interface serial data input input p20 si31 note 1 p34 so30 output serial interface serial data output input p21 so31 note 1 p35 sda0 note 2 i/o serial interface serial data input/output input p32 sck30 i/o serial interface serial clock input/output input p22 sck31 note 1 p36 scl0 note 2 p33 rxd0 input serial data input for asynchronous serial interface input p23 txd0 output serial data output for asynchronous serial interface input p24 asck0 input serial clock input for asynchronous serial interface input p25 ti00 input external count clock input to 16-bit timer/event counter 0 input p70/to0 capture trigger input to capture register 01 (cr01) of 16-bit timer/event counter 0 ti01 capture trigger input to capture register 00 (cr00) of 16-bit timer/event counter 0 p71 ti50 external count clock input to 8-bit timer/event counter 50 p72/to50 ti51 external count clock input to 8-bit timer/event counter 51 p73/to51 to0 output 16-bit timer/event counter 0 output input p70/ti00 to50 8-bit timer/event counter 50 output (also used for 8-bit pwm output) input p72/ti50 to51 8-bit timer/event counter 51 output (also used for 8-bit pwm output) p73/ti51 pcl output clock output (for trimming of main system clock and subsystem clock) input p74 buz output buzzer output input p75 ad0 to ad7 i/o lower address/data bus for expanding memory externally input p40 to p47 a8 to a15 output higher address bus for expanding memory externally input p50 to p57 rd output strobe signal output for reading from external memory input p64 wr strobe signal output for writing to external memory p65 wait input wait insertion at external memory access input p66 astb output strobe output that externally latches address information output to input p67 ports 4 and 5 to access external memory notes 1. si31, so31, and sck31 are incorporated only in the pd780024a subseries. 2. sda0 and scl0 are incorporated only in the pd780024ay subseries. .com .com .com .com 4 .com u datasheet
18 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds 3.2 non-port pins (2/2) pin name i/o function after alternate reset function ani0 to ani7 input a/d converter analog input input p10 to p17 adtrg input a/d converter trigger signal input input p03/intp3 av ref input a/d converter reference voltage input av dd a/d converter analog power supply. set potential to that of v dd0 or v dd1 av ss a/d converter ground potential. set potential to that of v ss0 or v ss1 reset input system reset input x1 input connecting crystal resonator for main system clock oscillation x2 xt1 input connecting crystal resonator for subsystem clock oscillation xt2 v dd0 positive power supply for ports v ss0 ground potential of ports v dd1 positive power supply (except ports) v ss1 ground potential (except ports) ic internally connected. connect directly to v ss0 or v ss1 . nc note not internally connected. leave open. note nc pins are incorporated only in the 73-pin plastic fbga. .com .com .com .com 4 .com u datasheet
19 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds 3.3 pin i/o circuits and recommended connection of unused pins the i/o circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the i/o circuit configuration of each type, see figure 3-1. table 3-1. types of pin i/o circuits pin name i/o i/o recommended connection of unused pins circuit type p00/intp0 to p02/intp2 8-c i/o input: independently connect to v ss0 or v ss1 via a resistor. p03/intp3/adtrg output: leave open. p10/ani0 to p17/ani7 25 input connect directly to v dd0 , v dd1 , v ss0 , or v ss1 via a resistor. p20/s130 8-c i/o input: independently connect to v dd0 , v dd1 , v ss0 , or v ss1 via p21/so30 5-h a resistor. p22/sck30 8-c output: leave open. p23/rxd0 p24/txd0 5-h p25/asck0 8-c p30, p31 13-q input: connect directly to v ss0 or v ss1 . p32, p33 13-s output: leave open at low-level output. ( pd780024a subseries only) p32/sda0 13-r ( pd780024ay subseries only) p33/scl0 ( pd780024ay subseries only) p34/si31 note 8-c input: independently connect to v dd0 , v dd1 , v ss0 , or v ss1 via p35/so31 note 5-h a resistor. p36/sck31 note 8-c output: leave open. p40/ad0 to p47/ad7 5-h input: independently connect to v dd0 or v dd1 via a resistor. output: leave open. p50/a8 to p57/a15 input: independently connect to v dd0 , v dd1 , v ss0 , or v ss1 via p64/rd a resistor. p65/wr output: leave open. p66/wait p67/astb p70/ti00/to0 8-c p71/ti01 p72/ti50/to50 p73/ti51/to51 p74/pcl 5-h p75/buz reset 2 input xt1 16 connect directly to v dd0 or v dd1 . xt2 leave open. av dd connect to directly v dd0 or v dd1 . av ref connect to directly v ss0 or v ss1 . av ss ic note si31, so31, and sck31 are incorporated only in the pd780024a subseries. .com .com .com .com 4 .com u datasheet
20 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds figure 3-1. pin i/o circuits type 2 schmitt-triggered input with hysteresis characteristics in type 8-c type 5-h data output disable p-ch in/out v dd0 n-ch input enable p-ch v dd0 pull-up enable type 13-q type 13-r data output disable in/out n-ch v dd0 mask option ? ? ? ? ? ? p-ch n-ch v ref (threshold voltage) v ss0 in data output disable in/out n-ch v ss0 type 25 data output disable in/out n-ch v ss0 v dd0 mask option ? ? ? ? ? ? .com .com .com .com 4 .com u datasheet
21 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds note the internal rom and internal high-speed ram capacities vary depending on the product (see the following table). part number last address of internal rom start address of internal high-speed ram nnnnh mmmmh 4. memory space figure 4-1 shows the memory map of the figure 4-1. memory map special function registers (sfr) 256 note reserved external memory internal rom note data memory space program memory space ffffh ff00h feffh fee0h fedfh mmmmh mmmmh 1 f7ffh nnnnh + 1 nnnnh 0000h program area callf entry area program area callt table area vector table area nnnnh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h f800h .com .com .com .com 4 .com u datasheet
22 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds 5. peripheral hardware function features 5.1 ports the following 3 types of i/o ports are available. cmos input (port 1): 8 cmos i/o (ports 0, 2, 4 to 7, p34 to p36): 39 n-channel open-drain i/o (p30 to p33): 4 total: 51 table 5-1. port functions name pin name function port 0 p00 to p03 i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. port 1 p10 to p17 input-only port. port 2 p20 to p25 i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. port 3 p30 to p33 n-channel open-drain i/o port. input/output can be specified in 1-bit units. a pull-up resistor can be specified by mask option. leds can be driven directly. p34 to p36 i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. port 4 p40 to p47 i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. the interrupt request flag (krif) is set to 1 by falling edge detection. port 5 p50 to p57 i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. leds can be driven directly. port 6 p64 to p67 i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. port 7 p70 to p75 i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. .com .com .com .com 4 .com u datasheet
23 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds 5.2 clock generator a system clock generator is incorporated. the minimum instruction execution time can be changed. expanded-specification products of pd780021a, 780022a, 780023a, 780024a 0.166 s/0.333 s/0.666 s/1.33 s/2.66 s (@12 mhz, v dd = 4.5 to 5.5 v operation with main system clock) 122 s (@32.768 khz, v dd = 4.0 to 5.5 v operation with subsystem clock) pd780021ay, 780022ay, 780023ay, 780024ay, and conventional products of pd780021a, 780022a, 780023a, 780024a 0.238 s/0.48 s/0.95 s/1.91 s/3.81 s (@8.38 mhz, v dd = 4.0 to 5.5 v operation with main system clock) 122 s (@32.768 khz, v dd = 4.0 to 5.5 v operation with subsystem clock) figure 5-1. clock generator block diagram xt1 xt2 x1 x2 f xt f x subsystem clock oscillator watch timer, clock output function prescaler main system clock oscillator clock to peripheral hardware cpu clock (f cpu ) standby controller wait controller 2 f x 2 2 f x 2 3 f x 2 4 f x f xt 2 prescaler selector stop 2 1 halt .com .com .com .com 4 .com u datasheet
24 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds 5.3 timer/counter five timer/counter channels are incorporated. 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel table 5-2. operations of timer/event counter 16-bit timer/ 8-bit timer/ watch timer watchdog timer event counter 0 event counters 50, 51 operation mode interval timer 1 channel 2 channels 1 channel note 1 1 channel note 2 external event counter 1 channel 2 channels function timer outputs 1 2 ppg outputs 1 pwm output 2 pulse width measurement 2 inputs square wave outputs 1 2 interrupt sources 2 2 2 1 notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer has watchdog timer and interval timer functions. however, use the watchdog timer by selecting either the watchdog timer function or the interval timer function. .com .com .com .com 4 .com u datasheet
25 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds figure 5-2. block diagram of 16-bit timer/event counter 0 internal bus ti01/p71 f x f x /2 2 f x /2 6 f x /2 3 ti00/to0/p70 note 16-bit capture/compare register 01 (cr01) match match 16-bit timer counter 0 (tm0) clear noise elimi- nator inttm00 to0/ti00/p70 note inttm01 internal bus selector 16-bit capture/compare register 00 (cr00) selector selector selector noise elimi- nator noise elimi- nator output controller note ti00 input and to0 output cannot be used at the same time. .com .com .com .com 4 .com u datasheet
26 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds figure 5-3. block diagram of 8-bit timer/event counter 50 figure 5-4. block diagram of 8-bit timer/event counter 51 internal bus 8-bit compare register 50 (cr50) ti50/to50/p72 f x /2 4 f x /2 6 f x /2 8 f x /2 10 f x f x /2 2 match mask circuit ovf clear 3 selector tcl502 tcl501 tcl500 timer clock selection register 50 (tcl50) internal bus tce50 tmc506 tmc504 lvs50 lvr50 tmc501 toe50 level inversion timer mode control register 50 (tmc50) s r s q r inv selector inttm50 to50/ti50/p72 selector 8-bit timer counter 50 (tm50) selector note 1 note 2 internal bus ti51/to51/p73 f x /2 3 f x /2 5 f x /2 7 f x /2 9 f x /2 11 f x /2 match mask circuit ovf clear 3 tcl512 tcl511 tcl510 timer clock selection register 51 (tcl51) internal bus tce51 tmc516 tmc514 lvs51 lvr51 tmc511 toe51 level inversion timer mode control register 51 (tmc51) s r q r inv selector inttm51 to51/ti51/p73 selector selector selector 8-bit compare register 51 (cr51) 8-bit timer counter 51 (tm51) s note 1 note 2 notes 1. timer output f/f 2. pwm output f/f .com .com .com .com 4 .com u datasheet
27 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds figure 5-5. watch timer block diagram figure 5-6. watchdog timer block diagram f x /2 7 f xt f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 wtm1 wtm0 watch timer mode control register (wtm) internal bus selector selector oscillation stabilization time selection register (osts) clock input controller intwdt reset wdt mode signal 3 osts2 osts1 osts0 wdcs2 wdcs1 wdcs0 internal bus divider divided clock selector output controller division mode selector run wdtm4 wdtm3 watchdog timer clock selection register (wdcs) watchdog timer mode register (wdtm) run f x /2 8 f x .com .com .com .com 4 .com u datasheet
28 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds 5.4 clock output/buzzer output controller a clock output/buzzer output controller is incorporated. clocks with the following frequencies can be output as clock output. expanded-specification products of pd780021a, 780022a, 780023a, 780024a 93.75 khz/187.5 khz/375 khz/750 khz/1.25 mhz/3 mhz/6 mhz/12 mhz (@12 mhz operation with main system clock) 32.768 khz (@32.768 khz operation with subsystem clock) pd780021ay, 780022ay, 780023ay, 780024ay, and conventional products of pd780021a, 780022a, 780023a, 780024a 65.5 khz/131 khz/262 khz/524 khz/1.05 mhz/2.10 mhz/4.19 mhz/8.38 mhz (@8.38 mhz operation with main system clock) 32.768 khz (@32.768 khz operation with subsystem clock) clocks with the following frequencies can be output as buzzer output. expanded-specification products of pd780021a, 780022a, 780023a, 780024a 1.46 khz/2.93 khz/5.86 khz/11.7 khz (@12 mhz operation with main system clock) pd780021ay, 780022ay, 780023ay, 780024ay, and conventional products of pd780021a, 780022a, 780023a, 780024a 1.02 khz/2.05 khz/4.10 khz/8.19 khz (@8.38 mhz operation with subsystem clock) figure 5-7. block diagram of clock output/buzzer output control circuit prescaler f x f xt 8 clock controller pcl/p74 buz/p75 4 f x to f x /2 7 f x /2 10 to f x /2 13 selector bcs0, bcs1 bzoe cloe bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 internal bus clock output selection register (cks) selector .com .com .com .com 4 .com u datasheet
29 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds 5.5 a/d converter an a/d converter consisting of eight 8-bit resolution channels is incorporated. the following two a/d conversion operation startup methods are available. hardware start software start figure 5-8. a/d converter block diagram tap selector intad av dd intp3 internal bus av ref a/d conversion result register (adcr0) controller successive approximation register (sar) edge detector ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 intp3/adtrg/p03 selector sample & hold circuit voltage comparator series resistor string edge detector av ss .com .com .com .com 4 .com u datasheet
30 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds 5.6 serial interface three serial interface channels are incorporated. pd780024a subseries serial interface uart0: 1 channel serial interface sio30, sio31: 2 channels pd780024ay subseries serial interface uart0: 1 channel serial interface sio30: 1 channel serial interface iic0 1 channel (1) serial interface uart0 serial interface uart0 has two modes: asynchronous serial interface (uart) mode and infrared data transfer mode. asynchronous serial interface (uart) mode this mode enables full-duplex operation wherein one byte of data starting from the start bit is transmitted and received. the on-chip uart-dedicated baud-rate generator enables communication using a wide range of selectable baud rates. in addition, a baud rate can also be defined by dividing the clock input to the asck0 pin. the uart-dedicated baud-rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). infrared data transfer mode this mode enables pulse output and pulse reception in data format. this mode can be used for office equipment applications such as personal computers. figure 5-9. block diagram of serial interface uart0 internal bus receive buffer register 0 rxb0 rxd0/p23 txd0/p24 receive shift register 0 pe0 fe0 ove0 asynchronous serial interface status register 0 (asis0) txs0 intser0 intst0 baud rate generator f x /2 to f x /2 7 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 asynchronous serial interface mode register 0 (asim0) intsr0 receive controller (parity check) transmit shift register 0 transmit controller (parity addition) rx0 p25/asck0 .com .com .com .com 4 .com u datasheet
31 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds (2) serial interface sio3n serial interface sio3n has one mode: 3-wire serial i/o mode. 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sck3n), serial output line (so3n), and serial input line (si3n). since simultaneous transmit and receive operations are enabled in the 3-wire serial i/o mode, the processing time for data transfer is reduced. the first bit in 8-bit data in the serial transfer is fixed as msb. the 3-wire serial i/o mode is useful for connection to peripheral i/o devices, and display controllers, etc., that include a clocked serial interface. figure 5-10. block diagram of serial interface sio3n remark pd780024a subseries: n = 0, 1 pd780024ay subseries: n = 0 internal bus 8 serial clock controller serial clock counter interrupt request signal generator selector serial i/o shift register 3n (sio3n) si3n so3n sck3n intcsi3n f x /2 3 f x /2 4 f x /2 5 .com .com .com .com 4 .com u datasheet
32 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds (3) serial interface iic0 ( pd780024ay subseries only) serial interface iic0 has one mode: i 2 c (inter ic) bus mode (supporting multimaster). ? 2 c bus mode (supporting multimaster) this is an 8-bit data transfer mode using two lines: a serial clock line (scl0) and a serial data bus line (sda0). this mode complies with the i 2 c bus format, and can output a start condition , data , and a stop condition during transmission via the serial data bus. this data is automatically detected by hardware during reception. since scl0 and sda0 are open-drain outputs in iic0, pull-up resistors for the serial clock line and the serial data bus line are required. figure 5-11. block diagram of serial interface iic0 internal bus iic status register 0 (iics0) iic control register 0 (iicc0) slave address register 0 (sva0) noise eliminator noise eliminator match signal iic shift register 0 (iic0) so0 latch iice0 d set clear cl00 sda0/p32 scl0/p33 n-ch open- drain output data hold time corrector acknowledge detector wake-up controller acknowledge detector stop condition detector serial clock counter interrupt request signal generator serial clock controller n-ch open-drain output serial clock wait controller prescaler intiic0 f x cld0 iic transfer clock select register 0 (iiccl0) internal bus lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 start condition detector dad0 smc0 dfc0 cl00 .com .com .com .com 4 .com u datasheet
33 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds 6. interrupt functions a total of 20 interrupt sources are provided, divided into the following three types. non-maskable: 1 maskable: 18 software: 1 table 6-1. interrupt source list interrupt default interrupt source internal/ type priority note 1 name trigger external non- intwdt watchdog timer overflow internal 0004h (a) maskable (with watchdog timer mode 1 selected) maskable 0 intwdt watchdog timer overflow (b) (with interval timer mode selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intser0 serial interface uart0 reception error internal 000eh (b) generation 6 intsr0 end of serial interface uart0 reception 0010h 7 intst0 end of serial interface uart0 transmission 0012h 8 intcsi30 end of serial interface sio30 transfer 0014h 9 intcsi31 end of serial interface sio31 transfer 0016h [only for pd780024a subseries] 10 intiic0 end of serial interface iic0 transfer 0018h [only for pd780024ay subseries] 11 intwti reference time interval signal from watch timer 001ah 12 inttm00 match between tm0 and cr00 001ch (when cr00 is specified as compare register) detection of ti01 valid edge (when cr00 is specified as capture register) 13 inttm01 match between tm0 and cr01 001eh (when cr01 is specified as compare register) detection of ti00 valid edge (when cr01 is specified as capture register) 14 inttm50 match between tm50 and cr50 0020h 15 inttm51 match between tm51 and cr51 0022h 16 intad0 end of a/d conversion 0024h 17 intwt watch timer overflow 0026h 18 intkr port 4 falling edge detection external 0028h (d) software brk brk instruction execution 003eh (e) notes 1. the default priority is the priority when several maskable interrupt requests are generated at the same time. 0 is the highest, and 18 is the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1. remark the watchdog timer interrupt (intwdt) can be selected from a non-maskable interrupt or a maskable interrupt (internal). basic configuration type note 2 vector table address .com .com .com .com 4 .com u datasheet
34 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds figure 6-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0 to intp3) internal bus priority controller vector table address generator standby release signal interrupt request mk internal bus ie pr isp if priority controller vector table address generator standby release signal interrupt request mk ie pr isp if priority controller vector table address generator external interrupt edge enable register (egp, egn) edge detector internal bus standby release signal interrupt request .com .com .com .com 4 .com u datasheet
35 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds figure 6-1. basic configuration of interrupt function (2/2) (d) external maskable interrupt (intkr) (e) software interrupt if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag mk ie pr isp if priority controller vector table address generator falling edge detector internal bus standby release signal interrupt request vector table address generator internal bus interrupt request .com .com .com .com 4 .com u datasheet
36 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds 7. external device expansion function the external device expansion function is for connecting external devices to areas other than the internal rom, ram, and sfr areas. ports 4 to 6 are used for external device connection. 8. standby function the following two standby modes are available for further reduction of system power consumption. halt mode: in this mode, the cpu operation clock is stopped. the average power consumption can be reduced by intermittent operation by combining this mode with the normal operation mode. stop mode: in this mode, oscillation of the main system clock is stopped. all the operations performed on the main system clock are suspended, and only the subsystem clock is used, resulting in extremely small power consumption. this can be used only when the main system clock is operating (the subsystem clock oscillation cannot be stopped). figure 8-1. standby function note the power consumption can be reduced by stopping the main system clock. when the cpu is operating on the subsystem clock, set bit 7 (mcc) of the processor clock control register (pcc). the stop instruction cannot be used. caution when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. 9. reset function the following two reset methods are available. external reset by reset signal input internal reset by watchdog timer program loop time detection 10. mask option table 10-1 pin mask option selection subseries name pins mask option pd780024a subseries p30 to p33 an on-chip pull-up resistor can be specified in 1-bit units. pd780024ay subseries p30 and p31 the mask option can be used to specify the connection of an on-chip pull-up resistor to p30 to p33 note , in 1-bit units. note the pd780024ay subseries has p30 and p31 only. main system clock operation stop mode main system clock operation is stopped interrupt request interrupt request halt instruction halt instruction interrupt request stop instruction css = 1 css = 0 subsystem clock operation note halt mode halt mode note clock supply for cpu is stopped, oscillation is maintained clock supply for cpu is stopped, oscillation is maintained .com .com .com .com 4 .com u datasheet
37 data sheet u14042ej4v0ds 11. instruction set (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz note except r = a 2nd operand 1st operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a r add addc sub subc and or xor cmp mov mov mov mov mov mov mov mov ror xch xch xch xch xch xch xch rol add add add add add rorc addc addc addc addc addc rolc sub sub sub sub sub subc subc subc subc subc and and and and and or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp mov mov add addc sub subc and or xor cmp inc dec b, c sfr mov mov mov mov dbnz mov add addc sub subc and or xor cmp saddr mov dbnz inc dec !addr16 mov psw push pop [de] ror4 mov [hl] mov rol4 [hl + byte] [hl + b] [hl + c] mov x c mulu divuw .com .com .com .com 4 .com u datasheet
38 data sheet u14042ej4v0ds (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw note only when rp = bc, de or hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop 2nd operand 1st operand ax rp sfrp saddrp !addr16 sp #word addw subw cmpw movw movw movw movw ax movw note movw movw movw movw movw rp note xchw sfrp movw saddrp movw !addr16 movw sp movw none incw, decw push, pop 2nd operand 1st operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy mov1 mov1 mov1 mov1 mov1 bt bf btclr bt bf btclr bt bf btclr bt bf btclr bt bf btclr set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 not1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 2nd operand 1st operand ax !addr16 !addr11 [addr5] $addr16 basic instruction compound instruction br call br callf callt br, bc, bnc bz, bnz bt, bf btclr dbnz .com .com .com .com 4 .com u datasheet
39 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds 12. electrical specifications 12.1 expanded-specification products of pd780021a, 780022a, 780023a, 780024a absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ?.3 to +6.5 v av dd ?.3 to v dd + 0.3 note v av ref ?.3 to v dd + 0.3 note v av ss ?.3 to +0.3 v input voltage v i1 p00 to p03, p10 to p17, p20 to p25, p34 to p36, p40 to p47, ?.3 to v dd + 0.3 note v p50 to p57, p64 to p67, p70 to p75, x1, x2, xt1, xt2, reset v i2 p30 to p33 n-ch open-drain without pull-up resistor ?.3 to + 6.5 v with pull-up resistor ?.3 to v dd + 0.3 note v output voltage v o ?.3 to v dd + 0.3 note v analog input voltage v an p10 to p17 analog input pin av ss ?0.3 to av ref0 + 0.3 note v and ?.3 to v dd + 0.3 note output current, i oh per pin ?0 ma high total for p00 to p03, p40 to p47, p50 to p57, p64 to p67, p70 to p75 ?5 ma total for p20 to p25, p30 to p36 ?5 ma output current, i ol per pin for p00 to p03, p20 to p25, p34 to 20 ma low p36, p40 to p47, p64 to p67, p70 to p75 per pin for p30 to p33, p50 to p57 30 ma total for p00 to p03, p40 to p47, 50 ma p64 to p67, p70 to p75 total for p20 to p25 20 ma total for p30 to p36 100 ma total for p50 to p57 100 ma operating ambient t a ?0 to +85 c temperature storage t stg ?5 to +150 c temperature note 6.5 v or below caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless otherwise specified, the characteristic of alternate-function pins are the same as those of port pins. .com .com .com .com 4 .com u datasheet
40 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds main system clock oscillator characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended parameter conditions min. typ. max. unit circuit ceramic oscillation 4.5 v v dd 5.5 v 1.0 12.0 mhz resonator frequency (f x ) note 1 3.0 v v dd < 4.5 v 1.0 8.38 1.8 v v dd < 3.0 v 1.0 5.0 oscillation after v dd reaches 4 ms stabilization time note 2 oscillation voltage range min. crystal oscillation 4.5 v v dd 5.5 v 1.0 12.0 mhz resonator frequency (f x ) note 1 3.0 v v dd < 4.5 v 1.0 8.38 1.8 v v dd < 3.0 v 1.0 5.0 oscillation 4.0 v v dd 5.5 v 10 ms stabilization time note 2 1.8 v v dd < 4.0 v 30 external x1 input 4.5 v v dd 5.5 v 1.0 12.0 mhz clock frequency (f x ) note 1 3.0 v v dd < 4.5 v 1.0 8.38 1.8 v v dd < 3.0 v 1.0 5.0 x1 input 4.5 v v dd 5.5 v 38 500 ns high-/low-level width 3.0 v v dd < 4.5 v 50 500 (t xh , t xl ) 1.8 v v dd < 3.0 v 85 500 notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. capacitance (t a = 25 c , v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. i/o c io f = 1 mhz p00 to p03, p20 to p25, 15 pf capacitance unmeasured pins p34 to p36, p40 to p47, returned to 0 v. p50 to p57, p64 to p67, p70 to p75 p30 to p33 20 pf remark unless otherwise specified, the characteristic of alternate-function pins are the same as those of port pins. c2 c1 x1 x2 ic c2 c1 x1 x2 ic x2 x1 .com .com .com .com 4 .com u datasheet
41 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds min. 32 32 resonator crystal resonator external clock parameter oscillation frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth , t xtl ) conditions 4.0 v v dd 5.5 v 1.8 v v dd < 4.0 v typ. 32.768 1.2 max. 35 2 10 38.5 unit khz s khz recommended circuit 12 15 s subsystem clock oscillator characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. remark for the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. c3 xt2 xt1 ic r c4 xt1 xt2 .com .com .com .com 4 .com u datasheet
42 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds recommended oscillator constant main system clock: ceramic resonator (t a = ?0 to +85 c) manufacturer part number frequency recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) r1 (k ? ) min. (v) max. (v) murata mfg. csbfb1m00j58 1.00 100 100 2.2 1.8 5.5 co., ltd. csbla1m00j58 1.00 100 100 2.2 1.8 5.5 cstcc2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstls2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstcc3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstls3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstcr4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstls4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstcr4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstls4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstcr4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstls4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstcr5m00g53 5.00 on-chip on-chip 0 1.8 5.5 cstls5m00g53 5.00 on-chip on-chip 0 1.8 5.5 cstce8m00g52 8.00 on-chip on-chip 0 3.0 5.5 cstls8m00g53 8.00 on-chip on-chip 0 3.0 5.5 cstce8m38g52 8.38 on-chip on-chip 0 3.0 5.5 cstls8m38g53 8.38 on-chip on-chip 0 3.0 5.5 cstce10m0g52 10.00 on-chip on-chip 0 4.5 5.5 cstls10m0g53 10.00 on-chip on-chip 0 4.5 5.5 cstce12m0g52 12.00 on-chip on-chip 0 4.5 5.5 cstla12m0t55 12.00 on-chip on-chip 0 4.5 5.5 tdk ccr3.58mc3 3.58 on-chip on-chip 0 1.8 5.5 ccr4.19mc3 4.19 on-chip on-chip 0 1.8 5.5 ccr5.0mc3 5.00 on-chip on-chip 0 1.8 5.5 ccr8.0mc5 8.00 on-chip on-chip 0 2.0 5.5 ccr8.38mc5 8.38 on-chip on-chip 0 2.0 5.5 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the pd780024a subseries within the specifications of the dc and ac characteristics. .com .com .com .com 4 .com u datasheet
43 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit output current, i oh per pin 1ma high all pins 15 ma output current, i ol per pin for p00 to p03, p20 to p25, p34 to p36, 10 ma low p40 to p47, p64 to p67, p70 to p75 per pin for p30 to p33, p50 to p57 15 ma total for p00 to p03, p40 to p47, p64 to p67, p70 to p75 20 ma total for p20 to p25 10 ma total for p30 to p36 70 ma total for p50 to p57 70 ma input voltage, v ih1 p10 to p17, p21, p24, p35, 2.7 v v dd 5.5 v 0.7v dd v dd v high p40 to p47, p50 to p57, 1.8 v v dd < 2.7 v 0.8v dd v dd v p64 to p67, p74, p75 v ih2 p00 to p03, p20, p22, p23, p25, 2.7 v v dd 5.5 v 0.8v dd v dd v p34, p36, p70 to p73, reset 1.8 v v dd < 2.7 v 0.85v dd v dd v v ih3 p30 to p33 2.7 v v dd 5.5 v 0.7v dd 5.5 v (n-ch open-drain) 1.8 v v dd < 2.7 v 0.8v dd 5.5 v v ih4 x1, x2 2.7 v v dd 5.5 v v dd 0.5 v dd v 1.8 v v dd < 2.7 v v dd 0.2 v dd v v ih5 xt1, xt2 4.0 v v dd 5.5 v 0.8v dd v dd v 1.8 v v dd < 4.0 v 0.9v dd v dd v input voltage, v il1 p10 to p17, p21, p24, p35, 2.7 v v dd 5.5 v 0 0.3v dd v low p40 to p47, p50 to p57, 1.8 v v dd < 2.7 v 0 0.2v dd v p64 to p67, p74, p75 v il2 p00 to p03, p20, p22, p23, p25, 2.7 v v dd 5.5 v 0 0.2v dd v p34, p36, p70 to p73, reset 1.8 v v dd < 2.7 v 0 0.15v dd v v il3 p30 to p33 4.0 v v dd 5.5 v 0 0.3v dd v 2.7 v v dd < 4.0 v 0 0.2v dd v 1.8 v v dd < 2.7 v 0 0.1v dd v v il4 x1, x2 2.7 v v dd 5.5 v 0 0.4 v 1.8 v v dd < 2.7 v 0 0.2 v v il5 xt1, xt2 4.0 v v dd 5.5 v 0 0.2v dd v 1.8 v v dd < 4.0 v 0 0.1v dd v output voltage, v oh1 4.0 v v dd 5.5 v, i oh = 1 ma v dd 1.0 v dd v high 1.8 v v dd < 4.0 v, i oh = 100 a v dd 0.5 v dd v output voltage, v ol1 p30 to p33 4.0 v v dd 5.5 v, 2.0 v low p50 to p57 i ol = 15 ma 0.4 2.0 v p00 to p03, p20 to p25, p34 to p36, 4.0 v v dd 5.5 v, 0.4 v p40 to p47, p64 to p67, p70 to p75 i ol = 1.6 ma v ol2 i ol = 400 a 0.5 v remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. .com .com .com .com 4 .com u datasheet
44 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p03, p10 to p17, p20 to p25, 3 a current, high p34 to p36, p40 to p47, p50 to p57, p60 to p67, p70 to p75, reset i lih2 x1, x2, xt1, xt2 20 a i lih3 v in = 5.5 v p30 to p33 note 3 a input leakage i lil1 v in = 0 v p00 to p03, p10 to p17, p20 to p25, 3 a current, low p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, reset i lil2 x1, x2, xt1, xt2 20 a i lil3 p30 to p33 note 3 a output leakage i loh v out = v dd 3 a current, high output leakage i lol v out = 0 v 3 a current, low mask option r 1 v in = 0 v, 15 30 90 k ? pull-up resistance p30, p31, p32, p33 software pull- r 2 v in = 0 v, 15 30 90 k ? up resistance p00 to p03, p20 to p25, p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75 note when pull-up resistors are not connected to p30 to p33 (specified by the mask option). remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. .com .com .com .com 4 .com u datasheet
45 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit power supply i dd1 note 2 12.0 mhz v dd = 5.0 v 10% note 3 when a/d converter is 8.5 17 ma current note 1 crystal oscillation stopped operating mode when a/d converter is 9.5 19 ma operating note 7 8.38 mhz v dd = 5.0 v 10% note 3 when a/d converter is 5.5 11 ma crystal oscillation stopped operating mode when a/d converter is 6.5 13 ma operating note 7 v dd = 3.0 v + 10% notes 3, 6 when a/d converter is 3 6 ma stopped when a/d converter is 4 8 ma operating note 7 5.00 mhz v dd = 3.0 v 10% note 3 when a/d converter is 2 4 ma crystal oscillation stopped operating mode when a/d converter is 3 6 ma operating note 7 v dd = 2.0 v 10% note 4 when a/d converter is 0.4 1.5 ma stopped when a/d converter is 1.4 4.2 ma operating note 7 i dd2 12.0 mhz v dd = 5.0 v 10% note 3 when peripheral functions 24ma crystal oscillation are stopped halt mode when peripheral functions 10 ma are operating 8.38 mhz v dd = 5.0 v 10% note 3 when peripheral functions 1.1 2.2 ma crystal oscillation are stopped halt mode when peripheral functions 4.7 ma are operating v dd = 3.0 v + 10% notes 3, 6 when peripheral functions 0.5 1 ma are stopped when peripheral functions 4ma are operating 5.00 mhz v dd = 3.0 v 10% note 3 when peripheral functions 0.35 0.7 ma crystal oscillation are stopped halt mode when peripheral functions 1.7 ma are operating v dd = 2.0 v 10% note 4 when peripheral functions 0.15 0.4 ma are stopped when peripheral functions 1.1 ma are operating i dd3 32.768 khz crystal oscillation v dd = 5.0 v 10% 40 80 a operating mode note 5 v dd = 3.0 v 10% 20 40 a v dd = 2.0 v 10% 10 20 a i dd4 32.768 khz crystal oscillation v dd = 5.0 v 10% 30 60 a halt mode note 5 v dd = 3.0 v 10% 6 18 a v dd = 2.0 v 10% 2 10 a i dd5 xt1 = v dd stop mode v dd = 5.0 v 10% 0.1 30 a when feedback resistor is not used v dd = 3.0 v 10% 0.05 10 a v dd = 2.0 v 10% 0.05 10 a .com .com .com .com 4 .com u datasheet
46 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds notes 1. total current through the internal power supply (v dd0 , v dd1 ) (except the current through pull-up resistors of ports). 2. i dd1 includes the peripheral operation current. 3. when the processor clock control register (pcc) is set to 00h. 4. when pcc is set to 02h. 5. when main system clock operation is stopped. 6. the values show the specifications when v dd = 3.0 to 3.3 v. the value in the typ. column show the specifications when v dd = 3.0 v. 7. includes the current through the av dd pin. .com .com .com .com 4 .com u datasheet
47 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej4v0ds ac characteristics (1) basic operation (t a = 40 to +85 parameter symbol conditions min. typ. max. unit cycle time t cy operating with 4.5 v v dd 5.5 v 0.166 16 s (min. instruction main system clock 3.0 v v dd 4.5 v 0.238 16 s execution time) 2.7 v v dd 3.0 v 0.4 16 s 1.8 v v dd 2.7 v 1.6 16 s operating with subsystem clock 103.9 note 1 122 125 s ti00, ti01 input t tih0 , t til0 3.0 v v dd 5.5 v 2/f sam +0.1 note 2 s high-/low-level 2.7 v v dd < 3.0 v 2/f sam +0.2 note 2 s width 1.8 v v dd < 2.7 v 2/f sam +0.5 note 2 s ti50, ti51 input f ti5 2.7 v v dd 5.5 v 0 4 mhz frequency 1.8 v v dd < 2.7 v 0 275 khz ti50, ti51 input t tih5 , t til5 2.7 v v dd 5.5 v 100 ns high-/low-level 1.8 v v dd < 2.7 v 1.8 ns width interrupt request t inth , t intl intp0 to intp3, 2.7 v v dd 5.5 v 1 s input high-/low- p40 to p47 1.8 v v dd < 2.7 v 2 s level width reset t rsl 2.7 v v dd 5.5 v 10 s low-level width 1.8 v v dd < 2.7 v 20 s notes 1. value when the external clock is used. when a crystal resonator is used, it is 114 s (min.). 2. selection of fsam = f x , f x /4, f x /64 is possible using bits 0 and 1 (prm00, prm01) of prescaler mode register 0 (prm0). however, if the ti00 valid edge is selected as the count clock, the value becomes fsam = f x /8. .com .com .com .com 4 .com u datasheet
48 data sheet u14042ej4v0ds t cy vs. v dd (main system clock operation) 5.0 1.0 2.0 1.6 0.4 0.238 0.166 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 1.8 5.5 2.7 4.5 operation guaranteed range 16.0 .com .com .com .com 4 .com u datasheet
49 data sheet u14042ej4v0ds (2) read/write operation (t a = 40 to +85 parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 20 ns address hold time t adh 6ns data input time from address t add1 (2 + 2n)t cy 54 ns t add2 (3 + 2n)t cy 60 ns address output time from rd t rdad 0 100 ns data input time from rd t rdd1 (2 + 2n)t cy 87 ns t rdd2 (3 + 2n)t cy 93 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 33 ns t rdl2 (2.5 + 2n)t cy 33 ns input time from rd to wait t rdwt1 t cy 43 ns t rdwt2 t cy 43 ns input time from wr to wait t wrwt t cy 25 ns wait low-level width t wtl (0.5 + n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 6ns wr low-level width t wrl1 (1.5 + 2n)t cy 15 ns delay time from astb to rd t astrd 6ns delay time from astb to wr t astwr 2t cy 15 ns delay time from t rdast 0.8t cy 15 1.2t cy ns rd to astb at external fetch address hold time from t rdadh 0.8t cy 15 1.2t cy + 30 ns rd at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 10 60 ns address hold time from wr t wradh 0.8t cy 15 1.2t cy + 30 ns delay time from wait to rd t wtrd 0.8t cy 2.5t cy + 25 ns delay time from wait to wr t wtwr 0.8t cy 2.5t cy + 25 ns caution t cy can only be used when the min. value is 0.238 t cy = t cy /4 2. n indicates the number of waits. 3 .c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.) (1/3) .com .com .com .com 4 .com u datasheet
50 data sheet u14042ej4v0ds (2/3) (2) read/write operation (t a = 40 to +85 parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 30 ns address hold time t adh 10 ns input time from address to data t add1 (2 + 2n)t cy 108 ns t add2 (3 + 2n)t cy 120 ns output time from rd to address t rdad 0 200 ns input time from rd to data t rdd1 (2 + 2n)t cy 148 ns t rdd2 (3 + 2n)t cy 162 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 40 ns t rdl2 (2.5 + 2n)t cy 40 ns input time from rd to wait t rdwt1 t cy 75 ns t rdwt2 t cy 60 ns input time from wr to wait t wrwt t cy 50 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 10 ns wr low-level width t wrl1 (1.5 + 2n)t cy 30 ns delay time from astb to rd t astrd 10 ns delay time from astb to wr t astwr 2t cy 30 ns delay time from t rdast 0.8t cy 30 1.2t cy ns rd to astb at external fetch hold time from t rdadh 0.8t cy 30 1.2t cy + 60 ns rd to address at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 20 120 ns hold time from wr to address t wradh 0.8t cy 30 1.2t cy + 60 ns delay time from wait to rd t wtrd 0.5t cy 2.5t cy + 50 ns delay time from wait to wr t wtwr 0.5t cy 2.5t cy + 50 ns caution t cy can only be used when the min. value is 0.4 t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, ad8 to ad15, rd, wr, wait, and astb pins.) .com .com .com .com 4 .com u datasheet
51 data sheet u14042ej4v0ds (3/3) (2) read/write operation (t a = 40 to +85 parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 120 ns address hold time t adh 20 ns input time from address to data t add1 (2 + 2n)t cy 233 ns t add2 (3 + 2n)t cy 240 ns output time from rd to address t rdad 0 400 ns input time from rd to data t rdd1 (2 + 2n)t cy 325 ns t rdd2 (3 + 2n)t cy 332 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 92 ns t rdl2 (2.5 + 2n)t cy 92 ns input time from rd to wait t rdwt1 t cy 350 ns t rdwt2 t cy 132 ns input time from wr to wait t wrwt t cy 100 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 20 ns wr low-level width t wrl1 (1.5 + 2n)t cy 60 ns delay time from astb to rd t astrd 20 ns delay time from astb to wr t astwr 2t cy 60 ns delay time from t rdast 0.8t cy 60 1.2t cy ns rd to astb at external fetch hold time from t rdadh 0.8t cy 60 1.2t cy + 120 ns rd to address at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 40 240 ns hold time from wr to address t wradh 0.8t cy 60 1.2t cy + 120 ns delay time from wait to rd t wtrd 0.5t cy 2.5t cy + 100 ns delay time from wait to wr t wtwr 0.5t cy 2.5t cy + 100 ns caution t cy can only be used when the min. value is 1.6 t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, ad8 to ad15, rd, wr, wait, and astb pins.) .com .com .com .com 4 .com u datasheet
52 data sheet u14042ej4v0ds (3) serial interface (t a = 40 to +85 parameter symbol conditions min. typ. max. unit sck3n t kcy1 4.5 v v dd 5.5 v 666 ns cycle time 3.0 v v dd < 4.5 v 954 ns 2.7 v v dd < 3.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns sck3n high-/ t kh1 , t kl1 3.0 v v dd 5.5 v t kcy1 /2 50 ns low-level width 1.8 v v dd < 3.0 v t kcy1 /2 100 ns si3n setup time t sik1 3.0 v v dd 5.5 v 100 ns (to sck3n ) 2.7 v v dd < 3.0 v 150 ns 1.8 v v dd < 2.7 v 300 ns si3n hold time t ksi1 4.5 v v dd 5.5 v 300 ns (from sck3n ) 1.8 v v dd < 4.5 v 400 ns delay time from t kso1 c = 100 pf note 4.5 v v dd 5.5 v 200 ns sck3n to so3n 1.8 v v dd < 4.5 v 300 ns output note c is the load capacitance of the sck3n and so3n output lines. (b) 3-wire serial i/o mode (sck3n... external clock input) parameter symbol conditions min. typ. max. unit sck3n t kcy2 4.5 v v dd 5.5 v 666 ns cycle time 3.0 v v dd < 4.5 v 800 ns 2.7 v v dd < 3.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns sck3n high-/ t kh2 , t kl2 4.5 v v dd 5.5 v 333 ns low-level width 3.0 v v dd < 4.5 v 400 ns 2.7 v v dd < 3.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns si3n setup time t sik2 100 ns (to sck3n ) si3n hold time t ksi2 4.5 v v dd 5.5 v 300 ns (from sck3n ) 1.8 v v dd < 4.5 v 400 ns delay time from t kso2 c = 100 pf note 4.5 v v dd 5.5 v 200 ns sck3n to so3n 1.8 v v dd < 4.5 v 300 ns output note c is the load capacitance of the so3n output line. remark n = 0, 1 .com .com .com .com 4 .com u datasheet
53 data sheet u14042ej4v0ds (c) uart mode (dedicated baud-rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.5 v v dd 5.5 v 187500 bps 3.0 v v dd < 4.5 v 131031 bps 2.7 v v dd < 3.0 v 78125 bps 1.8 v v dd < 2.7 v 39063 bps (d) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck0 cycle time t kcy3 4.0 v v dd 5.5 v 800 ns 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns asck0 high-/low-level width t kh3 , 4.0 v v dd 5.5 v 400 ns t kl3 2.7 v v dd < 4.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns transfer rate 4.0 v v dd 5.5 v 39063 bps 2.7 v v dd < 4.0 v 19531 bps 1.8 v v dd < 2.7 v 9766 bps (e) uart mode (infrared data transfer mode) parameter symbol conditions min. max. unit transfer rate 4.0 v v dd 5.5 v 131031 bps allowable bit rate error 4.0 v v dd 5.5 v 0.87 % output pulse width 4.0 v v dd 5.5 v 1.2 0.24/fbr note s input pulse width 4.0 v v dd 5.5 v 4/f x s note fbr: specified baud rate .com .com .com .com 4 .com u datasheet
54 data sheet u14042ej4v0ds a/d converter characteristics (t a = 40 to +85 parameter symbol conditions min. typ. max. unit resolution 888bit overall error note 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 1.8 v av ref < 2.7 v 1.2 %fsr conversion time t conv 4.5 v av dd 5.5 v 12 96 s 4.0 v av dd < 4.5 v 14 96 s 2.7 v av dd < 4.0 v 17 96 s 1.8 v av dd < 2.7 v 28 96 s analog input voltage v ian 0av ref v reference voltage av ref 1.8 av dd v resistance between av ref and av ss r ref when a/d converter not operating 20 40 k ? excludes quantization error ( 1/2 lsb). this value is indicated as a ratio (%fsr) to the full-scale value. remark the impedance of the analog input pins is shown below. [equivalent circuit] [parameter value] (typ.) av dd r1 r2 c1 c2 c3 2.7 v 12 k ? 8.0 k ? 3.0 pf 3.0 pf 2.0 pf 4.5 v 4 k ? 2.7 k ? 3.0 pf 1.4 pf 2.0 pf data memory stop mode low supply voltage data retention characteristics (t a = 40 to +85 parameter symbol conditions min. typ. max. unit data retention power v dddr 1.6 5.5 v supply voltage data retention power i dddr subsystem clock stop (xt1 = v dd ) and 0.1 30 a supply current feed-back resistor disconnected release signal set time t srel 0 s oscillation stabilization t wait release by reset 2 17 /fx s time release by interrupt request note s note selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible using bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts). c3 c2 r2 r1 c1 anin (n = 0 to 3) .com .com .com .com 4 .com u datasheet
55 data sheet u14042ej4v0ds 12.2 parameter symbol conditions ratings unit supply voltage v dd 0.3 to +6.5 v av dd 0.3 to v dd + 0.3 note v av ref 0.3 to v dd + 0.3 note v av ss 0.3 to +0.3 v input voltage v i1 p00 to p03, p10 to p17, p20 to p25, p34 to p36, p40 to p47, 0.3 to v dd + 0.3 note v p50 to p57, p64 to p67, p70 to p75, x1, x2, xt1, xt2, reset v i2 p30 to p33 n-ch open-drain without pull-up resistor 0.3 to + 6.5 v with pull-up resistor 0.3 to v dd + 0.3 note v output voltage v o 0.3 to v dd + 0.3 note v analog input voltage v an p10 to p17 analog input pin av ss 0.3 to av ref0 + 0.3 note v and 0.3 to v dd + 0.3 note output current, i oh per pin 10 ma high total for p00 to p03, p40 to p47, p50 to p57, p64 to p67, p70 to p75 15 ma total for p20 to p25, p30 to p36 15 ma output current, i ol per pin for p00 to p03, p20 to p25, p34 to 20 ma low p36, p40 to p47, p64 to p67, p70 to p75 per pin for p30 to p33, p50 to p57 30 ma total for p00 to p03, p40 to p47, 50 ma p64 to p67, p70 to p75 total for p20 to p25 20 ma total for p30 to p36 100 ma total for p50 to p57 100 ma operating ambient t a 40 to +85 c temperature storage t stg 65 to +150 c temperature note 6.5 v or below caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless otherwise specified, the characteristic of alternate-function pins are the same as those of port pins. .com .com .com .com 4 .com u datasheet
56 data sheet u14042ej4v0ds capacitance (t a = 25 parameter symbol conditions min. typ. max. unit input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. i/o c io f = 1 mhz p00 to p03, p20 to p25, 15 pf capacitance unmeasured pins p34 to p36, p40 to p47, returned to 0 v. p50 to p57, p64 to p67, p70 to p75 p30 to p33 20 pf remark unless otherwise specified, the characteristic of alternate-function pins are the same as those of port pins. resonator recommended parameter conditions min. typ. max. unit circuit ceramic oscillation 4.0 v v dd 5.5 v 1.0 8.38 mhz resonator frequency (f x ) note 1 1.8 v v dd < 4.0 v 1.0 5.0 oscillation after v dd reaches 4 ms stabilization time note 2 oscillation voltage range min. crystal oscillation 4.0 v v dd 5.5 v 1.0 8.38 mhz resonator frequency (f x ) note 1 1.8 v v dd < 4.0 v 1.0 5.0 oscillation 4.0 v v dd 5.5 v 10 ms stabilization time note 2 1.8 v v dd < 4.0 v 30 external x1 input 4.0 v v dd 5.5 v 1.0 8.38 mhz clock frequency (f x ) note 1 1.8 v v dd < 4.0 v 1.0 5.0 x1 input 4.0 v v dd 5.5 v 50 500 ns high-/low-level width 1.8 v v dd < 4.0 v 85 500 (t xh , t xl ) main system clock oscillator characteristics (t a = 40 to +85 indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. c2 c1 x1 x2 ic c2 c1 x1 x2 ic x2 x1 .com .com .com .com 4 .com u datasheet
57 data sheet u14042ej4v0ds min. 32 32 resonator crystal resonator external clock parameter oscillation frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth , t xtl ) conditions 4.0 v v dd 5.5 v 1.8 v v dd < 4.0 v typ. 32.768 1.2 max. 35 2 10 38.5 unit khz s khz recommended circuit 12 15 s subsystem clock oscillator characteristics (t a = 40 to +85 indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. remark for the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. c3 xt2 xt1 ic r c4 xt1 xt2 .com .com .com .com 4 .com u datasheet
58 data sheet u14042ej4v0ds recommended oscillator constant main system clock: ceramic resonator (t a = 40 to +85 manufacturer part number frequency recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) r1 (k ? ) min. (v) max. (v) murata mfg. csbfb1m00j58 1.00 100 100 2.2 1.8 5.5 co., ltd. csbla1m00j58 1.00 100 100 2.2 1.8 5.5 cstcc2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstls2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstcc3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstls3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstcr4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstls4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstcr4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstls4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstcr4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstls4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstcr5m00g53 5.00 on-chip on-chip 0 1.8 5.5 cstls5m00g53 5.00 on-chip on-chip 0 1.8 5.5 cstce8m00g52 8.00 on-chip on-chip 0 3.0 5.5 cstls8m00g53 8.00 on-chip on-chip 0 3.0 5.5 cstce8m38g52 8.38 on-chip on-chip 0 3.0 5.5 cstls8m38g53 8.38 on-chip on-chip 0 3.0 5.5 cstce10m0g52 10.00 on-chip on-chip 0 4.5 5.5 cstls10m0g53 10.00 on-chip on-chip 0 4.5 5.5 tdk ccr3.58mc3 3.58 on-chip on-chip 0 1.8 5.5 ccr4.19mc3 4.19 on-chip on-chip 0 1.8 5.5 ccr5.0mc3 5.00 on-chip on-chip 0 1.8 5.5 ccr8.0mc5 8.00 on-chip on-chip 0 2.0 5.5 ccr8.38mc5 8.38 on-chip on-chip 0 2.0 5.5 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the .com .com .com .com 4 .com u datasheet
59 data sheet u14042ej4v0ds dc characteristics (t a = 40 to +85 parameter symbol conditions min. typ. max. unit output current, i oh per pin 1ma high all pins 15 ma output current, i ol per pin for p00 to p03, p20 to p25, p34 to p36, 10 ma low p40 to p47, p64 to p67, p70 to p75 per pin for p30 to p33, p50 to p57 15 ma total for p00 to p03, p40 to p47, p64 to p67, p70 to p75 20 ma total for p20 to p25 10 ma total for p30 to p36 70 ma total for p50 to p57 70 ma input voltage, v ih1 p10 to p17, p21, p24, p35, 2.7 v v dd 5.5 v 0.7v dd v dd v high p40 to p47, p50 to p57, 1.8 v v dd < 2.7 v 0.8v dd v dd v p64 to p67, p74, p75 v ih2 p00 to p03, p20, p22, p23, p25, 2.7 v v dd 5.5 v 0.8v dd v dd v p34, p36, p70 to p73, reset 1.8 v v dd < 2.7 v 0.85v dd v dd v v ih3 p30 to p33 2.7 v v dd 5.5 v 0.7v dd 5.5 v (n-ch open-drain) 1.8 v v dd < 2.7 v 0.8v dd 5.5 v v ih4 x1, x2 2.7 v v dd 5.5 v v dd 0.5 v dd v 1.8 v v dd < 2.7 v v dd 0.2 v dd v v ih5 xt1, xt2 4.0 v v dd 5.5 v 0.8v dd v dd v 1.8 v v dd < 4.0 v 0.9v dd v dd v input voltage, v il1 p10 to p17, p21, p24, p35, 2.7 v v dd 5.5 v 0 0.3v dd v low p40 to p47, p50 to p57, 1.8 v v dd < 2.7 v 0 0.2v dd v p64 to p67, p74, p75 v il2 p00 to p03, p20, p22, p23, p25, 2.7 v v dd 5.5 v 0 0.2v dd v p34, p36, p70 to p73, reset 1.8 v v dd < 2.7 v 0 0.15v dd v v il3 p30 to p33 4.0 v v dd 5.5 v 0 0.3v dd v 2.7 v v dd < 4.0 v 0 0.2v dd v 1.8 v v dd < 2.7 v 0 0.1v dd v v il4 x1, x2 2.7 v v dd 5.5 v 0 0.4 v 1.8 v v dd < 2.7 v 0 0.2 v v il5 xt1, xt2 4.0 v v dd 5.5 v 0 0.2v dd v 1.8 v v dd < 4.0 v 0 0.1v dd v output voltage, v oh1 4.0 v v dd 5.5 v, i oh = 1 ma v dd 1.0 v dd v high 1.8 v v dd < 4.0 v, i oh = 100 a v dd 0.5 v dd v output voltage, v ol1 p30 to p33 4.0 v v dd 5.5 v, 2.0 v low p50 to p57 i ol = 15 ma 0.4 2.0 v p00 to p03, p20 to p25, p34 to p36, 4.0 v v dd 5.5 v, 0.4 v p40 to p47, p64 to p67, p70 to p75 i ol = 1.6 ma v ol2 i ol = 400 a 0.5 v remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. .com .com .com .com 4 .com u datasheet
60 data sheet u14042ej4v0ds dc characteristics (t a = 40 to +85 parameter symbol conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p03, p10 to p17, p20 to p25, 3 a current, high p34 to p36, p40 to p47, p50 to p57, p60 to p67, p70 to p75, reset i lih2 x1, x2, xt1, xt2 20 a i lih3 v in = 5.5 v p30 to p33 note 1 3 a input leakage i lil1 v in = 0 v p00 to p03, p10 to p17, p20 to p25, 3 a current, low p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, reset i lil2 x1, x2, xt1, xt2 20 a i lil3 p30 to p33 note 1 3 a output leakage i loh v out = v dd 3 a current, high output leakage i lol v out = 0 v 3 a current, low mask option r 1 v in = 0 v, 15 30 90 k ? pull-up resistance p30, p31, p32 note 2 , p33 note 2 software pull- r 2 v in = 0 v, 15 30 90 k ? up resistance p00 to p03, p20 to p25, p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75 notes 1. pd780021a, 780022a, 780023a, 780024a: when pull-up resistors are not connected to p30 to p33 (specified by the mask option). pd780021ay, 780022ay, 780023ay, 780024ay: when pull-up resistors are not connected to p30 and p31 (specified by the mask option). 2. only for the pd780021a, 780022a, 780023a, and 780024a. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. .com .com .com .com 4 .com u datasheet
61 data sheet u14042ej4v0ds dc characteristics (t a = 40 to +85 parameter symbol conditions min. typ. max. unit power supply i dd1 note 2 8.38 mhz v dd = 5.0 v 10% note 3 when a/d converter is 5.5 11 ma current note 1 crystal oscillation stopped operating mode when a/d converter is 6.5 13 ma operating note 6 5.00 mhz v dd = 3.0 v 10% note 3 when a/d converter is 2 4 ma crystal oscillation stopped operating mode when a/d converter is 3 6 ma operating note 6 v dd = 2.0 v 10% note 4 when a/d converter is 0.4 1.5 ma stopped when a/d converter is 1.4 4.2 ma operating note 6 i dd2 8.38 mhz v dd = 5.0 v 10% note 3 when peripheral functions 1.1 2.2 ma crystal oscillation are stopped halt mode when peripheral functions 4.7 ma are operating 5.00 mhz v dd = 3.0 v 10% note 3 when peripheral functions 0.35 0.7 ma crystal oscillation are stopped halt mode when peripheral functions 1.7 ma are operating v dd = 2.0 v 10% note 4 when peripheral functions 0.15 0.4 ma are stopped when peripheral functions 1.1 ma are operating i dd3 32.768 khz crystal oscillation v dd = 5.0 v 10% 40 80 a operating mode note 5 v dd = 3.0 v 10% 20 40 a v dd = 2.0 v 10% 10 20 a i dd4 32.768 khz crystal oscillation v dd = 5.0 v 10% 30 60 a halt mode note 5 v dd = 3.0 v 10% 6 18 a v dd = 2.0 v 10% 2 10 a i dd5 xt1 = v dd stop mode v dd = 5.0 v 10% 0.1 30 a when feedback resistor is not used v dd = 3.0 v 10% 0.05 10 a v dd = 2.0 v 10% 0.05 10 a notes 1. total current through the internal power supply (v dd0 , v dd1 ) (except the current through pull-up resistors of ports). 2. i dd1 includes the peripheral operation current. 3. when the processor clock control register (pcc) is set to 00h. 4. when pcc is set to 02h. 5. when main system clock operation is stopped. 6. includes the current through the av dd pin. .com .com .com .com 4 .com u datasheet
62 data sheet u14042ej4v0ds ac characteristics (1) basic operation (t a = 40 to +85 4.0 v v dd 5.5 v 2.7 v v dd < 4.0 v parameter symbol conditions min. typ. max. unit cycle time t cy operating with 0.238 16 s (min. instruction main system clock 0.4 16 s execution time) 1.6 16 s operating with subsystem clock 103.9 note 1 122 125 s ti00, ti01 input t tih0 , t til0 4.0 v v dd 5.5 v 2/f sam +0.1 note 2 s high-/low-level 2.7 v v dd < 4.0 v 2/f sam +0.2 note 2 s width 1.8 v v dd < 2.7 v 2/f sam +0.5 note 2 s ti50, ti51 input f ti5 2.7 v v dd 5.5 v 0 4 mhz frequency 1.8 v v dd < 2.7 v 0 275 khz ti50, ti51 input t tih5 , t til5 2.7 v v dd 5.5 v 100 ns high-/low-level 1.8 v v dd < 2.7 v 1.8 ns width interrupt request t inth , t intl intp0 to intp3, 2.7 v v dd 5.5 v 1 s input high-/low- p40 to p47 1.8 v v dd < 2.7 v 2 s level width reset t rsl 2.7 v v dd 5.5 v 10 s low-level width 1.8 v v dd < 2.7 v 20 s notes 1. value when the external clock is used. when a crystal resonator is used, it is 114 s (min.). 2. selection of f sam = f x , f x /4, f x /64 is possible using bits 0 and 1 (prm00, prm01) of prescaler mode register 0 (prm0). however, if the ti00 valid edge is selected as the count clock, the value becomes f sam = f x /8. 1.8 v v dd < 2.7 v .com .com .com .com 4 .com u datasheet
63 data sheet u14042ej4v0ds t cy vs. v dd (main system clock operation) 5.0 1.0 2.0 1.6 0.4 0.238 0.1 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 1.8 5.5 2.7 operation guaranteed range 16.0 cycle time t cy [ s] .com .com .com .com 4 .com u datasheet
64 data sheet u14042ej4v0ds (2) read/write operation (t a = 40 to +85 parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 20 ns address hold time t adh 6ns data input time from address t add1 (2 + 2n)t cy 54 ns t add2 (3 + 2n)t cy 60 ns address output time from rd t rdad 0 100 ns data input time from rd t rdd1 (2 + 2n)t cy 87 ns t rdd2 (3 + 2n)t cy 93 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 33 ns t rdl2 (2.5 + 2n)t cy 33 ns input time from rd to wait t rdwt1 t cy 43 ns t rdwt2 t cy 43 ns input time from wr to wait t wrwt t cy 25 ns wait low-level width t wtl (0.5 + n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 6ns wr low-level width t wrl1 (1.5 + 2n)t cy 15 ns delay time from astb to rd t astrd 6ns delay time from astb to wr t astwr 2t cy 15 ns delay time from t rdast 0.8t cy 15 1.2t cy ns rd to astb at external fetch address hold time from t rdadh 0.8t cy 15 1.2t cy + 30 ns rd at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 10 60 ns address hold time from wr t wradh 0.8t cy 15 1.2t cy + 30 ns delay time from wait to rd t wtrd 0.8t cy 2.5t cy + 25 ns delay time from wait to wr t wtwr 0.8t cy 2.5t cy + 25 ns caution t cy can only be used when the min. value is 0.238 t cy = t cy /4 2. n indicates the number of waits. 3 .c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.) (1/3) .com .com .com .com 4 .com u datasheet
65 data sheet u14042ej4v0ds (2/3) (2) read/write operation (t a = 40 to +85 parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 30 ns address hold time t adh 10 ns input time from address to data t add1 (2 + 2n)t cy 108 ns t add2 (3 + 2n)t cy 120 ns output time from rd to address t rdad 0 200 ns input time from rd to data t rdd1 (2 + 2n)t cy 148 ns t rdd2 (3 + 2n)t cy 162 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 40 ns t rdl2 (2.5 + 2n)t cy 40 ns input time from rd to wait t rdwt1 t cy 75 ns t rdwt2 t cy 60 ns input time from wr to wait t wrwt t cy 50 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 10 ns wr low-level width t wrl1 (1.5 + 2n)t cy 30 ns delay time from astb to rd t astrd 10 ns delay time from astb to wr t astwr 2t cy 30 ns delay time from t rdast 0.8t cy 30 1.2t cy ns rd to astb at external fetch hold time from t rdadh 0.8t cy 30 1.2t cy + 60 ns rd to address at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 20 120 ns hold time from wr to address t wradh 0.8t cy 30 1.2t cy + 60 ns delay time from wait to rd t wtrd 0.5t cy 2.5t cy + 50 ns delay time from wait to wr t wtwr 0.5t cy 2.5t cy + 50 ns caution t cy can only be used when the min. value is 0.4 t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, ad8 to ad15, rd, wr, wait, and astb pins.) .com .com .com .com 4 .com u datasheet
66 data sheet u14042ej4v0ds (3/3) (2) read/write operation (t a = 40 to +85 parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 120 ns address hold time t adh 20 ns input time from address to data t add1 (2 + 2n)t cy 233 ns t add2 (3 + 2n)t cy 240 ns output time from rd to address t rdad 0 400 ns input time from rd to data t rdd1 (2 + 2n)t cy 325 ns t rdd2 (3 + 2n)t cy 332 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 92 ns t rdl2 (2.5 + 2n)t cy 92 ns input time from rd to wait t rdwt1 t cy 350 ns t rdwt2 t cy 132 ns input time from wr to wait t wrwt t cy 100 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 20 ns wr low-level width t wrl1 (1.5 + 2n)t cy 60 ns delay time from astb to rd t astrd 20 ns delay time from astb to wr t astwr 2t cy 60 ns delay time from t rdast 0.8t cy 60 1.2t cy ns rd to astb at external fetch hold time from t rdadh 0.8t cy 60 1.2t cy + 120 ns rd to address at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 40 240 ns hold time from wr to address t wradh 0.8t cy 60 1.2t cy + 120 ns delay time from wait to rd t wtrd 0.5t cy 2.5t cy + 100 ns delay time from wait to wr t wtwr 0.5t cy 2.5t cy + 100 ns caution t cy can only be used when the min. value is 1.6 t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, ad8 to ad15, rd, wr, wait, and astb pins.) .com .com .com .com 4 .com u datasheet
67 data sheet u14042ej4v0ds (3) serial interface (t a = 40 to +85 parameter symbol conditions min. typ. max. unit sck3n t kcy1 4.0 v v dd 5.5 v 954 ns cycle time 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns sck3n high-/ t kh1 , t kl1 4.0 v v dd 5.5 v t kcy1 /2 50 ns low-level width 1.8 v v dd < 4.0 v t kcy1 /2 100 ns si3n setup time t sik1 4.0 v v dd 5.5 v 100 ns (to sck3n ) 2.7 v v dd < 4.0 v 150 ns 1.8 v v dd < 2.7 v 300 ns si3n hold time t ksi1 400 ns (from sck3n ) delay time from t kso1 c = 100 pf note 300 ns sck3n to so3n output note c is the load capacitance of the sck3n and so3n output lines. (b) 3-wire serial i/o mode (sck3n... external clock input) parameter symbol conditions min. typ. max. unit sck3n 4.0 v v dd 5.5 v 800 ns cycle time 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns sck3n high-/ t kh2 , t kl2 4.0 v v dd 5.5 v 400 ns low-level width 2.7 v v dd < 4.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns si3n setup time t sik2 100 ns (to sck3n ) si3n hold time t ksi2 400 ns (from sck3n ) delay time from t kso2 c = 100 pf note 300 ns sck3n to so3n output note c is the load capacitance of the so3n output line. remark conventional products of pd780021a, 780022a, 780023a, 780024a: n = 0 or 1 pd780021ay, 780022ay, 780023ay, 780024ay: n = 0 t kcy2 .com .com .com .com 4 .com u datasheet
68 data sheet u14042ej4v0ds (c) uart mode (dedicated baud-rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.0 v v dd 5.5 v 131031 bps 2.7 v v dd < 4.0 v 78125 bps 1.8 v v dd < 2.7 v 39063 bps (d) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck0 cycle time t kcy3 4.0 v v dd 5.5 v 800 ns 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns asck0 high-/low-level width t kh3 , 4.0 v v dd 5.5 v 400 ns t kl3 2.7 v v dd < 4.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns transfer rate 4.0 v v dd 5.5 v 39063 bps 2.7 v v dd < 4.0 v 19531 bps 1.8 v v dd < 2.7 v 9766 bps (e) uart mode (infrared data transfer mode) parameter symbol conditions min. max. unit transfer rate 4.0 v v dd 5.5 v 131031 bps allowable bit rate error 4.0 v v dd 5.5 v 0.87 % output pulse width 4.0 v v dd 5.5 v 1.2 0.24/fbr note s input pulse width 4.0 v v dd 5.5 v 4/f x s note fbr: specified baud rate .com .com .com .com 4 .com u datasheet
69 data sheet u14042ej4v0ds (f) i 2 c bus mode ( parameter symbol standard mode high-speed mode unit min. max. min. max. scl0 clock frequency f clk 0 100 0 400 kh z bus free time t buf 4.7 1.3 s (between stop and start conditions) hold time note 1 t hd:sta 4.0 0.6 s scl0 clock low-level width t low 4.7 1.3 s scl0 clock high-level width t high 4.0 0.6 s start/restart condition setup time t su:sta 4.7 0.6 s data hold time cbus-compatible master t hd:dat 5.0 s i 2 c bus 0 note 2 0 note 2 0.9 note 3 s data setup time t su:dat 250 100 note 4 ns sda0 and scl0 signal rise time t r 1000 20 + 0.1cb note 5 300 ns sda0 and scl0 signal fall time t f 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto 4.0 0.6 s spike pulse width controlled by input filter t sp 0 50 ns capacitive load per bus line cb 400 400 pf notes 1. in the start condition, the first clock pulse is generated after this hold time. 2. to fill in the undefined area of the scl0 falling edge, it is necessary for the device to internally provide at least 300 ns of hold time for the sda0 signal (which is v ihmin . of the scl0 signal). 3. if the device does not extend the scl0 signal low hold time (t low ), only the maximum data hold time t hd:dat needs to be fulfilled. 4. the high-speed mode i 2 c bus is available in a standard mode i 2 c bus system. at this time, the conditions described below must be satisfied. if the device does not extend the scl0 signal low state hold time t su:dat 250 ns if the device extends the scl0 signal low state hold time be sure to transmit the next data bit to the sda0 line before the scl0 line is released (t rmax . + t su:dat = 1000 + 250 = 1250 ns by standard mode i 2 c bus specification). 5. cb: total capacitance per bus line (unit: pf) .com .com .com .com 4 .com u datasheet
70 data sheet u14042ej4v0ds a/d converter characteristics (t a = 40 to +85 parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit overall error note 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 1.8 v av ref < 2.7 v 1.2 %fsr conversion time t conv 4.0 v av dd 5.5 v 14 96 s 2.7 v av dd < 4.0 v 19 96 s 1.8 v av dd < 2.7 v 28 96 s analog input voltage v ian 0av ref v reference voltage av ref 1.8 av dd v resistance between av ref and av ss r ref when a/d converter not operating 20 40 k ? excludes quantization error ( 1/2 lsb). this value is indicated as a ratio (%fsr) to the full-scale value. remark the impedance of the analog input pins is shown below. [equivalent circuit] [parameter value] (typ.) av dd r1 r2 c1 c2 c3 2.7 v 12 k ? 8.0 k ? 3.0 pf 3.0 pf 2.0 pf 4.5 v 4 k ? 2.7 k ? 3.0 pf 1.4 pf 2.0 pf data memory stop mode low supply voltage data retention characteristics (t a = 40 to +85 parameter symbol conditions min. typ. max. unit data retention power v dddr 1.6 5.5 v supply voltage data retention power i dddr subsystem clock stop (xt1 = v dd ) and 0.1 30 a supply current feed-back resistor disconnected release signal set time t srel 0 s oscillation stabilization t wait release by reset 2 17 /fx s time release by interrupt request note s note selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible using bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts). c3 c2 r2 r1 c1 anin (n = 0 to 3) .com .com .com .com 4 .com u datasheet
71 data sheet u14042ej4v0ds 12.3 timing chart ac timing test points (excluding x1, xt1 inputs) clock timing ti timing t xl t xh 1/f x v ih4 (min.) v il4 (max.) t xtl t xth 1/f xt v ih5 (min.) v il5 (max.) x1 input xt1 input t til0 t tih0 ti00, ti01 1/f t5 t tih5 t til5 ti50, ti51 0.8v dd 0.2v dd point of measurement 0.8v dd 0.2v dd .com .com .com .com 4 .com u datasheet
72 data sheet u14042ej4v0ds t rsl reset intp0 to intp3 t intl t inth interrupt request input timing reset input timing .com .com .com .com 4 .com u datasheet
73 data sheet u14042ej4v0ds read/write operation external fetch (no wait): external fetch (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdad t rdd1 instruction code t rdadh t rdast t astrd t rdl1 t rdh wait t rdwt1 t wtl t wtrd a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdd1 t rdad instruction code t rdadh t rdast t astrd t rdl1 t rdh .com .com .com .com 4 .com u datasheet
74 data sheet u14042ej4v0ds external data access (no wait): external data access (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 hi-z t ads t asth t adh t rdd2 t rdad read data t astrd t rdwd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 t ads t asth t adh t rdad t rdd2 read data t astrd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 t rdwt2 t wtl t wrwt t wtl t wtwr t wtrd wait t rdwd hi-z .com .com .com .com 4 .com u datasheet
75 data sheet u14042ej4v0ds serial transfer timing 3-wire serial i/o mode: .com .com .com .com 4 .com u datasheet
76 data sheet u14042ej4v0ds data retention timing (stop mode release by reset) t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr data retention timing (standby release signal: stop mode release by interrupt request signal) t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr .com .com .com .com 4 .com u datasheet
77 data sheet u14042ej4v0ds i j g h f d n m cb m r 64 33 32 1 l notes p64c-70-750a,c-4 item millimeters b c d f g h j k 1.778 (t.p.) 3.2 the external dimensions and materials of the es version are the same as those of the mass-produced version. .com .com .com .com 4 .com u datasheet
78 data sheet u14042ej4v0ds remark the external dimensions and materials of the es version are the same as those of the mass-produced version. 48 49 32 64 1 17 16 33 64-pin plastic qfp (14x14) note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.6 .com .com .com .com 4 .com u datasheet
79 data sheet u14042ej4v0ds 64-pin plastic lqfp (14x14) note each lead centerline is located within 0.20 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.2 + ? + ? + ? the external dimensions and materials of the es version are the same as those of the mass-produced version. .com .com .com .com 4 .com u datasheet
80 data sheet u14042ej4v0ds remark the external dimensions and materials of the es version are the same as those of the mass-produced version. 48 32 33 64 1 17 16 49 s s 64-pin plastic tqfp (12x12) item millimeters g 1.125 a 14.0 + ? + ? + ? .com .com .com .com 4 .com u datasheet
81 data sheet u14042ej4v0ds m 48 32 33 64 1 17 16 49 s n s j detail of lead end r k m i s l t p q g f h 64-pin plastic lqfp (10x10) item millimeters a b d g 12.0 + ? + ? the external dimensions and materials of the es version are the same as those of the mass-produced version. .com .com .com .com 4 .com u datasheet
82 data sheet u14042ej4v0ds b s a a b c d e f g h j s wb y1 s s wa s y s e x ba a1 a2 a b m ? the external dimensions and materials of the es version are the same as those of the mass-produced version. .com .com .com .com 4 .com u datasheet
83 data sheet u14042ej4v0ds 14. recommended soldering conditions this product should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. table 14-1. surface mounting type soldering conditions (1/3) (1) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-00-3 (at 210 c or higher), count: three times or less vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-3 (at 200 c or higher), count: three times or less wave soldering solder bath temperature: 260 c max., time: 10 seconds max., ws60-00-1 count: once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating). (2) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-00-2 (at 210 c or higher), count: two times or less vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-2 (at 200 c or higher), count: two times or less wave soldering solder bath temperature: 260 c max., time: 10 seconds max., ws60-00-1 count: once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating). .com .com .com .com 4 .com u datasheet
84 data sheet u14042ej4v0ds table 14-1. surface mounting type soldering conditions (2/3) (3) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-107-2 (at 210 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 seconds max. vp15-107-2 (at 200 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) wave soldering solder bath temperature: 260 c max., time: 10 seconds max., ws60-107-1 count: once, preheating temperature: 120 c max. (package surface temperature), exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) note after opening the dry pack, store it at 25 c or less and 65%rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). .com .com .com .com 4 .com u datasheet
85 data sheet u14042ej4v0ds table 14-1. surface mounting type soldering conditions (3/3) (4) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-00-2 (at 210 c or higher), count: twice or less vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-2 (at 200 c or higher), count: twice or less partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating). (5) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. ir60-203-3 (at 220 c or higher), count: three times or less, exposure limit: 3 days note (after that, prebake at 125 c for 20 hours) vps package peak temperature: 215 c, time: 40 seconds max. vp15-203-3 (at 200 c or higher), count: three times or less, exposure limit: 3 days note (after that, prebake at 125 c for 20 hours) note after opening the dry pack, store it at 25 c or less and 65%rh or less for the allowable storage period. caution do not use different soldering methods together. .com .com .com .com 4 .com u datasheet
86 data sheet u14042ej4v0ds table 14-2. insertion type soldering conditions soldering method soldering conditions wave soldering solder bath temperature: 260 c max., time: 10 seconds max. (only for pins) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution apply wave soldering only to the pins and be careful not to bring solder into direct contact with the package. .com .com .com .com 4 .com u datasheet
87 data sheet u14042ej4v0ds appendix a. development tools the following development tools are available for system development using the pd780024a, 780024ay subseries. also refer to (6) cautions on using development tools. (1) software package sp78k0 cd-rom in which various software tools for 78k/0 development are integrated in one package (2) language processing software ra78k0 assembler package common to 78k/0 series cc78k0 c compiler package common to 78k/0 series df780024 device file for pd780024a, 780024ay subseries cc78k0-l c compiler library source file common to 78k/0 series (3) flash memory writing tools flashpro iii (fl-pr3, pg-fp3) flash programmer dedicated to microcontrollers with on-chip flash memory flashpro iv (fl-pr4, pg-fp4) fa-64cw adapter for flash memory writing used connected to the flashpro iii/flashpro iv. fa-64gc fa-64cw: 64-pin plastic sdip (cw type) fa-64gc-8bs-a fa-64gc: 64-pin plastic qfp (gc-ab8 type) fa-64gk-9et fa-64gc-8bs-a: 64-pin plastic lqfp (gc-8bs type) fa-64gb-8eu fa-64gk-9et: 64-pin plastic tqfp (gk-9et type) fa-73f1-cn3-a fa-64gb-8eu: 64-pin plastic lqfp (gb-8eu type) fa-73f1-cn3-a: 73-pin plastic fbga (f1-cn3 type) .com .com .com .com 4 .com u datasheet
88 data sheet u14042ej4v0ds (4) debugging tools when using in-circuit emulator ie-78k0-ns or ie-78k0-ns-a ie-78k0-ns in-circuit emulator common to 78k/0 series ie-78k0-ns-pa performance board to enhance and expand the functions of ie-78k0-ns ie-78k0-ns-a combination of ie-78k-ns and ie-78k0-ns-pa ie-70000-mc-ps-b power supply unit for ie-78k0-n and ie-78k0-ns-a ie-70000-98-if-c adapter required when using pc-9800 series as host machine (excluding notebook pcs) (c bus supported) ie-70000-cd-if-a pc card and interface cable when using notebook pc as host machine (pcmcia socket supported) ie-70000-pc-if-c adapter required when using ibm pc/at tm or compatible as host machine (isa bus supported) ie-70000-pci-if-a adapter required when using pc in which pci bus is incorporated as host machine ie-780034-ns-em1 emulation board to emulate pd780024a, 780024ay subseries np-64cw emulation probe for 64-pin plastic sdip (cw type) np-h64cw np-64gc emulation probe for 64-pin plastic qfp (gc-ab8 type), 64-pin plastic lqfp (gc-8bs type) np-64gc-tq np-h64gc-tq np-64gk emulation probe for 64-pin plastic tqfp (gk-9et type) np-h64gk-tq np-h64gb-tq emulation probe for 64-pin plastic lqfp (gb-8eu type) np-73f1-cn3 note emulation probe for 73-pin plastic fbga (f1-cn3 type) ev-9200gc-64 conversion socket to connect the np64gc and a target system board on which a 64-pin plastic qfp (gc-ab8 type), 64-pin plastic lqfp (gc-8bs type) can be mounted. tgc-064sap conversion adapter to connect the np-64gc-tq or np-h64gc-tq and a target system board on which a 64-pin plastic qfp (gc-ab8 type), 64-pin plastic lqfp (gc-8bs type) can be mounted tgk-064sbw conversion adapter to connect the np-64gk or np-h64gk-tq and a target system on which a 64- pin plastic tqfp (gk-9et type) can be mounted tgb-064sdp conversion socket to connect the np-h64gb-tq and a target system board on which a 64-pin plastic lqfp (gb-8eu type) can be mounted csice73a0909n01, conversion socket to connect the np-73f1-cn3 and a target system board on which a 73-pin plastic lspack73a0909n01, fbga (f1-cn3 type) can be mounted cssocket73a0909n01 id78k0-ns integrated debugger for ie-78k0-ns and ie-78k0-ns-a sm78k0 system simulator common to 78k/0 series df780024 device file for pd780024a, 780024ay subseries note the conversion socket (csice73a0909n01, lspack73a0909n01, or cssocket73a0909n01) is supplied with the emulation probe (np-73f1-cn3). .com .com .com .com 4 .com u datasheet
89 data sheet u14042ej4v0ds when using in-circuit emulator ie-78001-r-a ie-78001-r-a in-circuit emulator common to 78k/0 series ie-70000-98-if-c adapter required when using pc-9800 series as host machine (excluding notebook pcs) (c bus supported) ie-70000-pc-if-c interface adapter when using ibm pc/at or compatible as host machine (isa bus supported) ie-70000-pci-if-a adapter required when using pc in which pci bus is incorporated as host machine ie-780034-ns-em1 emulation board to emulate pd780024a, 780024ay subseries ie-78k0-r-ex1 emulation probe conversion board necessary when using ie-780034-ns-em1 on ie-78001-r-a ep-78240cw-r emulation probe for 64-pin plastic sdip (cw type) ep-78240gc-r emulation probe for 64-pin plastic qfp (gc-ab8 type) ep-78012gk-r emulation probe for 64-pin plastic tqfp (gk-9et type) ev-9200gc-64 conversion socket to connect the ep-78240gc-r a nd a target system board on which a 64-pin plastic qfp (gc-ab8 type) can be mounted tgk-064sbw conversion adapter to connect the ep-78012gk-r a nd a target system board on which a 64-pin plastic tqfp (gk-9et type) can be mounted id78k0 integrated debugger for ie-78001-r-a sm78k0 system simulator common to 78k/0 series df780024 device file for pd780024a, 780024ay subseries (5) real-time os rx78k0 real-time os for 78k/0 series caution the 64-pin plastic lqfp (gb-8eu type) and 73-pin plastic fbga (f1-cn3 type) do not support the ie-78001-r-a. .com .com .com .com 4 .com u datasheet
90 data sheet u14042ej4v0ds (6) cautions on using development tools the id78k0-ns, id78k0, and sm78k0 are used in combination with the df780024. the cc78k0 and rx78k0 are used in combination with the ra78k0 and the df780024. fl-pr3, fl-pr4, fa-64cw, fa-64gc, fa-64gc-8bs-a, fa-64gk-9et, fa-64gb-8eu, fa-73f1-cn3-a, np-64cw, np-h64cw, np-64gc, np-64gc-tq, np-h64gc-tq, np-64gk, np-h64gk-tq, np-h64gb-tq, and np-73f1-cn3 are products made by naito densei machida mfg. co., ltd. (+81-45-475-4191). tgc-064sap, tgk-064sbw, tgb-064sdp, csice73a0909n01, lspack73a0909n01, and cssocket73a0909n01 are products made by tokyo eletech corporation. refer to: daimaru kogyo, ltd. tokyo electronic division (+81-3-3820-7112) osaka electronic division (+81-6-6244-6672) for third-party development tools, see the single-chip microcontroller development tool selection guide (u11069e) . the host machines and oss supporting each software are as follows. host machine pc ews [os] pc-9800 series [japanese windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at and compatibles sparcstation tm [sunos tm , solaris tm ] software [japanese/english windows] ra78k0 cc78k0 id78k0-ns id78k0 sm78k0 rx78k0 dos-based software .com .com .com .com 4 .com u datasheet
91 data sheet u14042ej4v0ds appendix b. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd780024a, 780034a, 780024ay, 780034ay subseries user s manual u14046e pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay this document data sheet pd780021a(a), 780022a(a), 780023a(a), 780024a(a), 780021ay(a), 780022ay(a), 780023ay(a), u15131e 780024ay(a) data sheet pd78f0034a, 78f0034ay data sheet u14040e pd78f0034b, 78f0034by, 78f0034b(a), 78f0034by(a) data sheet to be prepared 78k/0 series instructions user s manual u12326e documents related to development software tools (user s manuals) document name document no. ra78k0 assembler package operation u14445e language u14446e structured assembly language u11789e cc78k0 c compiler operation u14297e language u14298e sm78k series system simulator ver. 2.30 or later operation (windows based) u15373e external part user open interface specifications u15802e id78k series integrated debugger ver. 2.30 or later operation (windows based) u15185e rx78k0 real-time os fundamentals u11537e installation u11536e project manager ver. 3.12 or later (windows based) u14610e documents related to development hardware tools (user s manuals) document name document no. ie-78k0-ns in-circuit emulator u13731e ie-78k0-ns-a in-circuit emulator u14889e ie-780034-ns-em1 emulation board u14642e ie-78001-r-a in-circuit emulator u14142e ie-78k0-r-ex1 in-circuit emulator to be prepared caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. .com .com .com .com 4 .com u datasheet
92 data sheet u14042ej4v0ds documents related to flash memory writing document name document no. pg-fp3 flash memory programmer user s manual u13502e pg-fp4 flash memory programmer user s manual u15260e other related documents document name document no. semiconductor selection guide - products & packages - x13769e semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. .com .com .com .com 4 .com u datasheet
93 data sheet u14042ej4v0ds [memo] .com .com .com .com 4 .com u datasheet
94 data sheet u14042ej4v0ds notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. note: purchase of nec electronics l 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. fip and iebus are trademarks of nec electronics corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united status and/ or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. .com .com .com .com 4 .com u datasheet
95 data sheet u14042ej4v0ds regional information ? ? ? ? ? ? sucursal en espa ? a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v ? lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 succursale fran ? aise filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 tyskland filial taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: .com .com .com .com 4 .com u datasheet
these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. ? ? ? ? ? ? .com .com .com 4 .com u datasheet

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